OR3LP26B datasheet(40/184 Pages) AGERE

40 / 184 page

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Master Write, Burst Transaction

Figure 4 (FPGA bus) and Figure 5 (PCI bus) show the timing of a four Quadword Master write burst transaction.

Operation is similar to that in the previous Master write, nonburst transaction, but extra data is supplied by the

FPGA application. In Figure 4, the transaction is initiated by the FPGA application asserting Master address enable

(maenn), while providing the command word and address on bus datafmfpga. On the second through fifth clocks,

maenn is deasserted, the Master write data enable (mwdataenn) is asserted, and four Quadwords of data are

provided on bus datafmfpga. Since the protocol for providing start-up data is fixed for a specific operation, the

FPGA application can be preprogrammed with the sequence, or can use the value of the Master state counter

(mstatecntr) to assist in determination of the next required Quadword of information. The PCI core knows that this

is a burst operation because the FPGA application deasserts the Master write burst signal (mwlastcycn) during all

but the final data transfer cycle. Execution begins on the PCI bus, as shown in Figure 5. If the Master write PCI bus

hold signal (mwpcihold) is inactive, PCI bus activity will begin when the Master write FIFO goes nonempty; other-

wise, the PCI bus activity will wait until all data is loaded, as in this case, or the FIFO goes full. Execution begins on

the PCI bus, as shown in Figure 5.

5-8832(F).a

Figure 4. Master Write 32-Byte Burst (FPGA Bus, Dual-Port)

CMD

ADRS

fclk

ma_fulln

mstatecntr

mcmd

datafmfpga

maenn

mwdataenn

mwlastcycn

mw_fulln

mw_afulln

mwpcihold

OR3LP26B Datasheet(PDF) 40 Page - Agere Systems