OR3LP26B datasheet(114/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

114

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Target Read I/O, Delayed Transaction

Figure 40 (PCI bus) and Figure 43 (FPGA bus) show the timing for a Target I/O read that is handled as a delayed

transaction. In other words, the operation completes on the local (FPGA) bus before completing on the PCI bus.

The FPGA application indicates its desire to do this by driving the delayed transaction signal deltrn active-low. In

Figure 40, three transactions are shown: the first is the initial read that latches the command, address, and byte

enables. The PCI core’s Target logic then issues a retry, obligating the remote Master to continue to issue that iden-

tical request until data is moved. Meanwhile, the latched information is relayed to the FPGA interface via the

address FIFO, triggering the FPGA interface exchange discussed below and in Figure 43. All subsequent read or

write requests to memory or I/O space will result in retries, as shown in the second transaction of Figure 40. The

third transaction is the final transaction that completes the transfer of data. The timing on this third transaction is

identical to the timing of the first except that trdyn accompanies stopn to indicate the disconnect with data.

The timing on the FPGA interface (Figure 40) shows that the first indication to the FPGA application that a new

operation has begun is the assertion of Target request (treqn), together with the new command on bus twdata.

The FPGA application responds by asserting Target address enable (taenn) and accepting the command and

lower DWORD address on bus twdata, after which taenn is deasserted. On the next clock, the upper DWORD

address is transferred. The FPGA application then accesses the requested data, asserts Target read data enable

(trdataenn), and transmits the data on bus trdata.

5-8858(F).a

Figure 40. Target I/O Read, Delayed (PCI Bus, 64-Bit)

Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

ADRS

DATA

CMD

BEs

CMD

BEs

CMD

BEs

clk

framen

c_ben

irdyn

trdyn

stopn

evseln

TRANSACTION #1: ADDRESS, BYTE ENABLES,

AND COMMAND LATCHED AS A

DELAYED READ REQUEST.

TRANSACTION #2: DISCONNECTED W/O DATA

BECAUSE READ OPERATION NOT COMPLETED.

TRANSACTION #3: DISCONNECTED WITH DATA

BECAUSE READ OPERATION COMPLETED.

OR3LP26B Datasheet(PDF) 114 Page - Agere Systems

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