STM8S003K3 datasheet(77/100 Pages) STMICROELECTRONICS

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Figure 36: Typical NRST pull-up current vs VDD @ 4 temperatures

The reset network shown in the following figure protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see

#unique_55/CD662 ), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be

reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,

attention must be taken to the charge/discharge time of the external capacitor to fulfill the

external devices reset timing conditions. Minimum recommended capacity is 10 nF.

Figure 37: Recommended reset pin protection

0.1 µF

External

reset

circuit

STM8

Filter

RPU

VDD

Internal reset

NRST

(optional)

SPI serial peripheral interface

9.3.8

Unless otherwise specified, the parameters given in the following table are derived from tests

performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions.

tMASTER = 1/fMASTER.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

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Electrical characteristics

STM8S003K3 STM8S003F3

STM8S003K3 Datasheet(PDF) 77 Page - STMicroelectronics