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TFRA08C13 Datasheet(PDF) 21 Page - Agere Systems |
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TFRA08C13 Datasheet(HTML) 21 Page - Agere Systems |
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21 / 188 page  Lucent Technologies Inc. 21 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent Technologies Inc. Pins Symbol Type* Description D2 TFS[1] O Transmit Framer Frame Sync. This signal is the 8 kHz frame synchro- nization pulse in the transmit framer. This signal is active-high. P2 TFS[2] Y3 TFS[3] AE13 TFS[4] AA24 TFS[5] M25 TFS[6] C22 TFS[7] B8 TFS[8] B1 TFDLCK[1] O Transmit Facility Data Link Clock. In DS1-DDS with data link access, this is an 8 kHz clock signal; otherwise, 4 kHz. The transmit frame latches data link bits on the falling edge of TFDLCK. M4 TFDLCK[2] AA2 TFDLCK[3] AE12 TFDLCK[4] Y26 TFDLCK[5] L25 TFDLCK[6] D20 TFDLCK[7] B7 TFDLCK[8] B3 TFDL[1] I Transmit Facility Data Link. Optional serial input facility data link bit stream inserted into the transmit line data stream by the transmit framer. In DS1-DDS with data link access, this is an 8 kbits/s signal; otherwise, 4 kbits/s. In the CEPT frame format, TFDL can be pro- grammed to one of the XSa bits of the NOT FAS frame time slot 0. N2 TFDL[2] W3 TFDL[3] AF11 TFDL[4] Y24 TFDL[5] M24 TFDL[6] C21 TFDL[7] D8 TFDL[8] C5 RCHIDATA[1] I Receive CHI Data. Serial input system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. L3 RCHIDATA[2] Y1 RCHIDATA[3] AD10 RCHIDATA[4] W25 RCHIDATA[5] L26 RCHIDATA[6] A21 RCHIDATA[7] A7 RCHIDATA[8] * Iu indicates an internal pull-up, Id indicates an internal pull-down. † After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state. Pin Information (continued) Table 2. Pin Descriptions (continued) |
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