TFRA08C13 datasheet(22/188 Pages) AGERE

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Preliminary Data Sheet

TFRA08C13 OCTAL T1/E1 Framer

October 2000

Lucent Technologies Inc.

Pin Information (continued)

Table 2. Pin Descriptions (continued)

Pins

Symbol

Type*

Description

RCHIDATAB[1]

Receive CHI Data B. Serial input system data at 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s.

RCHIDATAB[2]

RCHIDATAB[3]

AE11

RCHIDATAB[4]

V23

RCHIDATAB[5]

M23

RCHIDATAB[6]

B20

RCHIDATAB[7]

RCHIDATAB[8]

G23

LORLCK

Loss of Receive Clock. This pin is asserted high (logic 1) when RLCK

in the receive framer does not toggle for a 250

µs interval. Once

asserted, this signal is deasserted on the first edge of RLCK (See Table

66. Global Control Register (GREG8) (008)).

RLCK[1]

Receive Framer Line Interface Clock. This is the 1.544 MHz DS1 or

2.048 MHz input clock signal used by the receive framer to latch RPD

and RND data.

RLCK[2]

AF4

RLCK[3]

AF20

RLCK[4]

AF21

RLCK[5]

U24

RLCK[6]

G24

RLCK[7]

C13

RLCK[8]

RPD[1]

Receive Positive-Rail Data. NRZ serial data latched by the rising edge

of RLCK. Data rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. Optional

single-rail NRZ receive data latched by the rising edge of RLCK.

RPD[2]

RPD[3]

AF10

RPD[4]

W24

RPD[5]

J26

RPD[6]

C20

RPD[7]

RP81]

RND[1]

Receive Negative-Rail Data. Nonreturn-to-zero (NRZ) serial data

latched by the rising edge of RLCK. Data rates: DS1-1.544 Mbits/s;

CEPT-2.048 Mbits/s. In the single-rail mode, when RND = 1 the receive

bipolar violation counter increments once for each rising edge of RLCK.

RND[2]

RND[3]

AD9

RN[4]

V25

RND[5]

H25

RND[6]

B19

RND[7]

RND[8]

* Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

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