PCAL9538A

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 2 — 10 December 2012

14 of 43

NXP Semiconductors

PCAL9538A

Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge

phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port

register).

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and

actual data transfer from P port (see Figure 9).

Fig 11. Read Input port register (latch enabled)

1100

A1 A0

1

A

S1

slave address

START condition

R/W

acknowledge from slave

002aah106

data from port

A

acknowledge from master

SDA

1

no acknowledge

from master

read from

port

data into

port

data from port

DATA 1

DATA 1

INT

DATA 2

DATA 2

P

STOP

condition

12345678

SCL

9

DATA 1

INT is cleared by

read from port

STOP not needed

to clear INT