LR8809 datasheet(4/7 Pages) LRC

4 / 7 page

V0.3

4(7)

CE8809 C/N 20～26

3.0

13.0

—

CE8809 C/N 26～39

3.0

15.0

—

NMOS：

VOUT =0.5 V

VDD =－VDET－0.5 V

CE8809 C/N 39～60

3.0

18.0

—

CE8809 C/N 20～26

1.5

4.0

—

CE8809 C/N 26～39

1.5

6.0

—

Output

current

IOUT

PMOS：

VDD－VOUT =0.5 V

VDD =－VDET＋0.5 V

CE8809 C/N 39～60

1.5

8.0

—

Leakage

current

ILEAK

Only for NMOS open-drain output products,

VDD =8.0 V, VOUT =8.0 V

—

0.1

temperature

coefficient

Ta=−40°C ~ +85°C

—

±120

±360

ppm/

°C

Delay time

200

*1. −VDET: Actual detection voltage value, −VDET(S): Specified detection voltage value

Functional Description

1. When a voltage higher than the release voltage (+VDET) is applied to the voltage input

pin (VDD), the voltage will gradually fall..When a voltage higher than the detect voltage

(-VDET) is applied to VDD , output (VOUT) will be equal to the input at VDD.

Note that high impedance exists at VOUT with the N-channel open drain configuration. If

the pin is pulled up, VOUT T will be equal to the pull up voltage.

2. When VDD falls below -VDET , VOUT will be equal to the ground voltage (VSS) level

(detect state).

Note that this also applies to N-channel open drain configurations.

3. When VDD falls to a level below that of the minimum operating voltage (VMIN ) output

will become unstable.

Because the output pin is generally pulled up with N-channel open drain configurations,

output will be equal to pull up voltage.

4. When VDD rises above the VSS level (excepting levels lower than minimum operating

voltage), VOUT will be equal to VSS until VDD reaches the +VDET level.

5 . Although VDD will rise to a level higher than +VDET, VOUT maintains ground voltage

level via the delay circuit.

Following transient delay time, VDD will be output at VOUT.

Note that high impedance exists with the N-channel open drain configuration and that

voltage will be dependent on pull up.

Notes :

1. The difference between -VDET and +VDET represents the hysteresis range.

2. Propagation delay time (tD) represents the time it takes for VDD to appear at VOUT

once the said voltage has exceeded the +VDET level.

LRC

LESHAN RADIO COMPANY,LTD.

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