MPC993

3

MOTOROLA

ECLinPS and ECLinPS Lite

DL140 — Rev 3

3.3V PECL AC Characteristics (TA = 0°C to 85°C)

Symbol

Parameter

Min

Typ

Max

Unit

fVCO

Maximum VCO Frequency

480

MHz

tpwi

25

75

%

tpd

Propagation Delay (Note 1.)

CLKn to Q (Bypass)

CLKn to Q (Locked (Note 2.))

X–500

Y–150

2000

0

X+500

Y+150

ps

tr/tf

Output Rise/Fall Time

200

800

ps

tskew

Output Skew

Within Bank

All Outputs

50

100

ps

∆pe

Maximum Phase Error Deviation

TBD (Note 3.)

TBD (Note 4.)

ps

∆per/cycle

Rate of Change of Periods

75MHz Output (Note 3.)

150MHz Output (Note 3.)

75MHz Output (Note 4.)

150MHz Output (Note 4.)

20

10

TBD

TBD

ps

tpw

Output Duty Cycle

45

55

%

tjitter

Cycle–to–Cycle Jitter

50

ps

tlock

Maximum PLL Lock Time

10

ms

1. These values represent simulation results. Final values will be determined from silicon measurements and may be adjusted slightly.

2. Static phase offset between the selected reference clock and the feedback signal.

3. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over

the clock switch excursion. (See Applications Information section on page 4 for more detail)

4. Specification holds for a clock switch between two signals no greater than

±π out of phase. Delta period change per cycle is averaged over the

clock switch excursion.

PIN DESCRIPTIONS

Pin Name

I/O

Pin Definition

CLK0, CLK0

CLK1, CLK1

LVPECL Input

LVPECL Input

Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)

Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)

Ext_FB, Ext_FB

LVPECL Input

Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)

Qa0:1, Qa0:1

LVPECL Output

Differential 1x output pairs

Qb0:2, Qb0:2

LVPECL Output

Differential 2x output pairs

Inp0bad

LVCMOS Output

Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output

is active HIGH and will remain HIGH until the alarm reset is asserted

Inp1bad

LVCMOS Output

Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output

is active HIGH and will remain HIGH until the alarm reset is asserted

Clk_Selected

LVCMOS Output

‘0’ if clock 0 is selected, ‘1’ if clock 1 is selected

Alarm_Reset

LVCMOS Input

‘0’ will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one–shotted”

(75

Ω pullup)

Sel_Clk

LVCMOS Input

‘0’ selects CLK0, ‘1’ selects CLK1 (75

Ω pulldown)

Manual_Override

LVCMOS Input

‘1’ disables internal clock switch circuitry (75

Ω pulldown)

PLL_En

LVCMOS Input

‘0’ bypasses selected input reference around the phase–locked loop (75

Ω pulldown)

MR

LVCMOS Input

‘0’ resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (75

Ω pullup)

VCCA

Power Supply

PLL power supply

VCC

Power Supply

Digital power supply

GNDA

Power Supply

PLL ground

GND

Power Supply

Digital ground