MCP4531 datasheet(15/102 Pages) MICROCHIP

15 / 102 page

 2008-2013 Microchip Technology Inc.

DS22096B-page 15

MCP453X/455X/463X/465X

103B

(Note 5)

TFSDA

SDA fall time

100 kHz mode

—

300

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mode

20 + 0.1Cb

(Note 3)

300

1.7 MHz mode

160

3.4 MHz mode

106

THD:DAT

Data input hold

time

100 kHz mode

—

1.8V-5.5V, Note 5

400 kHz mode

—

2.7V-5.5V, Note 5

1.7 MHz mode

—

4.5V-5.5V, Note 5

3.4 MHz mode

—

4.5V-5.5V, Note 5

107

TSU:DAT Data input setup

time

100 kHz mode

250

—

Note 2

400 kHz mode

100

—

1.7 MHz mode

—

3.4 MHz mode

—

109

TAA

Output valid

from clock

100 kHz mode

—

3450

Note 1

400 kHz mode

—

900

1.7 MHz mode

—

150

Cb = 100 pF,

Note 1, Note 6

—

310

Cb = 400 pF,

Note 1, Note 4

3.4 MHz mode

—

150

Cb = 100 pF, Note 1

110

TBUF

Bus free time

100 kHz mode

4700

—

Time the bus must be free

before a new transmission

can start

400 kHz mode

1300

—

1.7 MHz mode

N.A.

—

3.4 MHz mode

N.A.

—

TSP

Input filter spike

suppression

(SDA and SCL)

100 kHz mode

—

Philips Spec states N.A.

400 kHz mode

—

1.7 MHz mode

—

Spike suppression

3.4 MHz mode

—

Spike suppression

TABLE 1-2:

I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I2C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40

C  T

A  +125C (Extended)

Operating Voltage VDD range is described in AC/DC Characteristics

Param.

No.

Symbol Characteristic

Min

Max

Units

Conditions

Note 1:

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the

requirement tSU;DAT  250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line.

TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I

2C bus specification) before

the SCL line is released.

Use Cb in pF for the calculations.

Not tested.

A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

Ensured by the TAA 3.4 MHz specification test.

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