QG5000XSL9TH datasheet(45/458 Pages) INTEL

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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet

expansion bus is physically attached to the Intel 631xESB/632xESB I/O Controller Hub

and, from a configuration perspective, appears to be a hierarchical PCI bus behind a

PCI-to-PCI bridge; therefore, it has a programmable PCI Bus number.

The MCH contains 14 PCI devices within a single physical component. The configuration

registers for these devices are mapped as devices residing on PCI bus 0.

• Device 0: ESI bridge/PCI Express Port 0. Logically, this appears as a PCI device

that resides on PCI bus 0. Physically Device 0, Function 0 contains the PCI Express

configuration registers for the ESI port, and other MCH specific registers.

• Device 2: PCI Express 2. Logically this appears as a PCI device residing on bus 0.

Device 2, Function 0 is routed to the PCI Express configuration registers for PCI

Express port 2. When PCI Express ports 2 and 3 are combined into a single x8 port,

controlled by port 2 registers, Device 3, Function 0 (port 3) configuration registers

are inactive. PCI Express port 2 resides at DID of 25E2h(x4) or 25F7h(x8).

• Device 3: PCI Express 3. Logically this appears as a PCI device that resides on bus

0. Device 3, Function 0 contains the PCI Express configuration registers for PCI

Express port 3. When PCI Express ports 2 and 3 are combined into a single x8 port,

controlled by port 2 registers, these configuration registers are inactive. PCI

Express port 3 resides at DID of 25E3h.

• Device 4: PCI Express 4. Logically this appears as a PCI device that resides on bus

0. Device 4, Function 0 contains the PCI Express configuration registers for PCI

Express port 4. When PCI Express ports 4, 5, 6, and 7 are combined into a single

x16 graphics port, Device 4, Function 0 contains the configuration registers and

Device 5, Function 0 (port 5), Device 6, Function 0 (port 6), and Device 7, Function

0 (port 7), configuration registers are inactive. PCI Express port 4 resides at DID of

25E4h(x4) or 25F8h(x8) or 25FAh(x16).

• Device 5: PCI Express 5. Logically this appears as a PCI device that resides on bus

0. Device 5, Function 0 contains the PCI Express configuration registers for PCI

Express port 5. When PCI Express ports 4, 5, 6 and 7 are combined into a single

x16 graphics port Device 4, Function 0 contains the configuration registers, and

these configuration registers are inactive. PCI Express port 5 resides at DID of

25E5h.

• Device 6: PCI Express 6. Logically this appears as a PCI device residing on bus 0.

Device 6, Function 0 contains the PCI Express configuration registers for PCI

Express port 6. When PCI Express ports 4, 5, 6 and 7 are combined into a single

x16 graphics port Device 4, Function 0 contains the configuration registers, and

these configuration registers are inactive. PCI Express port 6 resides at DID of

25E6h(x4) or 25F9(x8).

• Device 7: PCI Express 7. Logically this appears as a PCI device residing on bus 0.

Device 7, Function 0 contains the PCI Express configuration registers for PCI

Express port 7. When PCI Express ports 4, 5, 6 and 7 are combined into a single

x16 graphics port Device 4, Function 0 contains the configuration registers, and

these configuration registers are inactive. PCI Express port 2 resides at DID of

25E7h.

• Device 9: Device 9, Function 0 is routed to the Advanced Memory Buffer memory

map. This interface is supported through the JTAG and SMBus interfaces and

AMBSELECT register only.

• Device 16: Device 16, Function 0 is routed to the Frontside Bus (FSB) Controller,

Interrupt and System Address registers. Function 1 is routed to the Frontside Bus

Address Mapping, Memory Control, and Error registers. Function 2 is routed to FSB

Error Registers. These devices reside at DID 25F0h.

QG5000XSL9TH Datasheet(PDF) 45 Page - Intel Corporation

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