FV08KM202 datasheet(3/336 Pages) MICROCHIP

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 2013 Microchip Technology Inc.

Advance Information

DS33030A-page 3

PIC24FV16KM204 FAMILY

Special Microcontroller Features

• Wide Operating Voltage Range Options:

- 1.8V to 3.6V (PIC24F devices)

- 2.0V to 5.0V (PIC24FV devices)

• Selectable Power Management modes:

- Idle: CPU shuts down, allowing for significant

power reduction

- Sleep: CPU and peripherals shut down for

substantial power reduction and fast wake-up

- Retention Sleep mode: PIC24FV devices can

enter Sleep mode, employing the

retention regulator, further reducing power

consumption

- Doze: CPU can run at a lower frequency than

peripherals, a user-programmable feature

- Alternate Clock modes allow on-the-fly

switching to a lower clock speed for selective

power reduction

• Fail-Safe Clock Monitor:

- Detects clock failure and switches to on-chip,

low-power RC oscillator

• Ultra Low-Power Wake-up Pin Provides an

External Trigger for Wake from Sleep

• 10,000 Erase/Write Cycle Endurance Flash

Program Memory, Typical

• 100,000 Erase/Write Cycle Endurance

Data EEPROM, Typical

• Flash and Data EEPROM Data Retention: 20 Years

Minimum

• Self-Programmable under Software Control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its Own On-Chip

RC Oscillator for Reliable Operation

• On-Chip Regulator for 5V Operation

• Selectable Windowed WDT Feature

• Selectable Oscillator Options including:

- 4x Phase Locked Loop (PLL)

• 8 MHz (FRC) Internal RC Oscillator:

- HS/EC, high-speed crystal/resonator

oscillator or external clock

• In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Emulation (ICE) – via Two Pins

• In-Circuit Debugging

• Programmable High/Low-Voltage

Detect (HLVD) module

• Programmable Brown-out Reset (BOR):

- Software enable feature

- Configurable shutdown in Sleep

- Auto-configures power mode and sensitivity

based on device operating speed

- LPBOR available for re-arming of the POR

High-Performance RISC CPU

• Modified Harvard Architecture

• Operating Speed:

- DC – 32 MHz clock input

- 16 MIPS at 32 MHz clock input

• 8 MHz Internal Oscillator:

- 4x PLL option

- Multiple clock divide options

- Fast start-up

• 17-Bit x 17-Bit Single-Cycle Hardware

Fractional/Integer Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16 x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture

• 24-Bit-Wide Instructions

• 16-Bit-Wide Data Path

• Linear Program Memory Addressing, up to

6 Mbytes

• Linear Data Memory Addressing, up to 64 Kbytes

• Two Address Generation Units (AGUs) for Separate

Read and Write Addressing of Data Memory

Peripheral Features

• High-Current Sink/Source, 18 mA/18 mA All Ports

• Independent Ultra Low-Power, 32 kHz

Timer Oscillator

• Up to Two Master Synchronous Serial Ports

(MSSPs) with SPI and I2C™ modes:

In SPI mode:

- User-configurable SCKx and SDOx pin outputs

- Daisy-chaining of SPI slave devices

In I2C mode:

- Serial clock synchronization (clock stretching)

- Bus collision detection and will arbitrate

accordingly

- Support for 16-bit read/write interface

• Up to Two Enhanced Addressable UARTs:

- LIN/J2602 bus support (auto-wake-up,

Auto-Baud Detect, Break character support)

- High and low speed (SCI)

-IrDA® mode (hardware encoder/decoder

function)

• Two External Interrupt Pins

• Hardware Real-Time Clock and Calendar (RTCC)

• Configurable Reference Clock Output (REFO)

• Two Configurable Logic Cells (CLC)

• Up to Two Single Output Capture/Compare/PWM

(SCCP) modules and up to Three Multiple Output

Capture/Compare/PWM (MCCP) modules

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