ADAU1461WBCPZ-R7 datasheet(13/88 Pages) AD

13 / 88 page

ADAU1461

Rev. 0 | Page 13 of 88

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

IOVDD

MCLK

ADDR0/CLATCH

JACKDET/MICIN

MICBIAS

LAUX

AVDD

24 DVDDOUT

23 AVDD

22 AGND

21 MONOOUT

20 LHP

19 RHP

18 LOUTP

17 LOUTN

TOP VIEW

(Not to Scale)

ADAU1461

NOTES

1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE

ADAU1461 GROUNDS. FOR INCREASED RELIABILITY OF THE

SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS

RECOMMENDED THAT THE PAD BE SOLDERED TO THE

GROUND PLANE.

Figure 7. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

IOVDD

PWR

Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,

which also sets the highest input voltage that should be seen on the digital input pins.

IOVDD should be set to 3.3 V. The current draw of this pin is variable because it is dependent

on the loads of the digital outputs. IOVDD should be decoupled to DGND with a 100 nF

capacitor and a 10 μF capacitor.

MCLK

D_IN

External Master Clock Input.

ADDR0/CLATCH

D_IN

I2C Address Bit 0 (ADDR0).

SPI Latch Signal (CLATCH). Must go low at the beginning of an SPI transaction and high at the

end of a transaction. Each SPI transaction can take a different number of CCLKs to complete,

depending on the address and read/write bit that are sent at the beginning of the SPI

transaction.

JACKDET/MICIN

D_IN

Detect Insertion/Removal of Headphone Plug (JACKDET).

Digital Microphone Stereo Input (MICIN).

MICBIAS

A_OUT

Bias Voltage for Electret Microphone.

LAUX

A_IN

Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2.

A_OUT

AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF standard decoupling capacitor should

be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs.

This pin can be used to bias external analog circuits, as long as they are not drawing current

from CM (for example, the noninverting input of an op amp).

AVDD

PWR

3.3 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled locally to

AGND with a 100 nF capacitor.

AGND

PWR

Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.

AGND should be decoupled locally to AVDD with a 100 nF capacitor.

LINP

A_IN

Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2.

LINN

A_IN

Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2.

RINP

A_IN

Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2.

RINN

A_IN

Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2.

RAUX

A_IN

Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2.

ROUTP

A_OUT

Right Line Output, Positive. Biased at AVDD/2.

ROUTN

A_OUT

Right Line Output, Negative. Biased at AVDD/2.

LOUTN

A_OUT

Left Line Output, Negative. Biased at AVDD/2.

LOUTP

A_OUT

Left Line Output, Positive. Biased at AVDD/2.

ADAU1461WBCPZ-R7 Datasheet(PDF) 13 Page - Analog Devices

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