DAC8420FSZ2 datasheet(16/24 Pages) AD

16 / 24 page

DAC8420

Rev. B | Page 16 of 24

VREFHI INPUT REQUIREMENTS

The DAC8420 utilizes a unique, patented DAC switch driver

circuit that compensates for different supply, reference voltage,

and digital code inputs. This ensures that all DAC ladder switches

are always biased equally, ensuring excellent linearity under all

conditions. Thus, as shown in Table 1, the VREFHI input of the

DAC8420 requires both sourcing and sinking current capabili-

ties from the reference voltage source. Many positive voltage

references are intended as current sources only and offer little

sinking capability. The user should consider references such as

the AD584, AD586, AD587, AD588, AD780, and REF43 for

such an application.

POWER-UP SEQUENCE

To prevent a CMOS latch-up condition, power up VDD, VSS,

and GND prior to any reference voltages. The ideal power-up

sequence is GND, VSS, VDD, VREFHI, VREFLO, and digital

inputs. Noncompliance with the power-up sequence over an

extended period can elevate the reference currents and eventually

damage the device. On the other hand, if the noncompliant

power-up sequence condition is as short as a few milliseconds,

the device can resume normal operation without being damaged

once VDD/VSS is powered.

DAC8420FSZ2 Datasheet(PDF) 16 Page - Analog Devices