4

8

12

16

20

24

28

32

36

0

5

10

15

20

25

30

35

Operating Region

Vout

R2

FBx

GND

R1

LM5642, LM5642X

www.ti.com

SNVS219K – JUNE 2003 – REVISED APRIL 2013

Figure 31. Output Voltage Setting

Example: Vnom = 5V, Vfb = 1.2364V, Ifbmax = 200nA.

(8)

Choose 60K

(9)

The Cycle Skip and Dropout modes of the LM5642 series regulate the minimum and maximum output

voltage/duty cycle that the converter can deliver. Both modes check the voltage at the COMP pin. Minimum

output voltage is determined by the Cycle Skip Comparator. This circuitry skips the high side FET ON pulse

when the COMP pin voltage is below 0.5V at the beginning of a cycle. The converter will continue to skip every

other pulse until the duty cycle (and COMP pin voltage) rise above 0.5V, effectively halving the switching

frequency.

Maximum output voltage is determined by the Dropout circuitry, which skips the low side FET ON pulse

whenever the COMP pin voltage exceeds the ramp voltage derived from the current sense. Up to three low side

pulses may be skipped in a row before a minimum on-time pulse must be applied to the low side FET.

Figure 32 shows the range of ouput voltage (for Io = 3A) with respect to input voltage that will keep the converter

from entering either Skip Cycle or Dropout mode.

For input voltages below 5.5V, VLIN5 must be connected to Vin through a small resistor (approximately 4.7

ohm). This will ensure that VLIN5 does not fall below the UVLO threshold.

Figure 32. Output Voltage Range

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