TSB81BA3DI datasheet(15/61 Pages) TI1

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TSB81BA3D, TSB81BA3DI

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

Table 1. Base Register Configuration

Address

BIT POSITION

Address

0000

Physical ID

CPS

0001

RHB

IBR

Gap_Count

0010

Extended (111b)

Num_Ports (0011b)

0011

PHY_Speed (111b)

Rsvd

Delay (0000b)

0100

LCtrl

Jitter (000b)

Pwr_Class

0101

WDIE

ISBR

CTOI

CPSI

STOI

PEI

EAA

EMC

0110

Max Legacy SPD

BLINK

Bridge

Rsvd

0111

Page_Select

Rsvd

Port_Select

Table 2. Base Register Field Descriptions

FIELD

SIZE

TYPE

DESCRIPTION

Physical ID

This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid after

a bus reset until the self-ID has completed as indicated by an unsolicited register 0 status transfer from the PHY

to the LLC.

Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during

tree-ID if this node becomes root.

CPS

Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to

serial bus cable power through a 400-k

Ω resistor. A 0 in this bit indicates that the cable power voltage has

dropped below its threshold for ensured reliable operation.

RHB

Rd/Wr

Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit is reset

to 0 by a hardware reset, and is unaffected by a bus reset. If two nodes on a single bus have their root holdoff bit

set, then the result is not defined. To prevent two nodes from having their root-holdoff bit set, this bit must only be

written using a PHY configuration packet.

IBR

Rd/Wr

Initiate bus reset. This bit instructs the PHY to initiate a long (166

μs) bus reset at the next opportunity. Any

receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR

bit is reset to 0 after a hardware reset or a bus reset. Care must be exercised when writing to this bit to not change

the other bits in this register. It is recommended that whenever possible a bus reset be initiated using the ISBR bit

and not the IBR bit.

Gap_Count

Rd/Wr

Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count

can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap

count is reset to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap

count register (either by a write to the PHY register or by a PHY_CONFIG packet). It is strongly recommended

that this field only be changed using PHY configuration packets.

Extended

Extended register definition. For the TSB81BA3D, this field is 111b, indicating that the extended register set is

implemented.

Num_Ports

Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB81BA3D this field

is 3.

PHY_Speed

PHY speed capability. This field is no longer used. For the TSB81BA3D PHY this field is 111b. Speeds for 1394b

PHYs must be checked on a port-by-port basis.

Delay

PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY, expressed as

144+(delay

× 20) ns. For the TSB81BA3D this field is 02h.

This value is the repeater delay for the S400B case, which is slower than the S800B or 1394a cases. Since the

IEEE 1394B−2002 Std Phy register set only has a single field for the delay parameter, the slowest value is used.

If a network uses only S800B or 1394a connections, then a delay value of 00h may be used. The worst case Phy

repeater delay is 197 ns for S400B and 127 ns for S800B cable speeds (trained, raw bit speed).

TSB81BA3DI Datasheet(PDF) 15 Page - Texas Instruments

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