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PI7C8140AMAE Datasheet(PDF) 7 Page - Pericom Semiconductor Corporation |
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PI7C8140AMAE Datasheet(HTML) 7 Page - Pericom Semiconductor Corporation |
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7 / 82 page  PI7C8140A 2-PORT PCI-TO-PCI BRIDGE Page 7 of 82 March 20, 2007 – Revision 1.01 13.1 REGISTER TYPES ...............................................................................................................................59 13.2 CONFIGURATION REGISTER...........................................................................................................59 13.2.1 VENDOR ID REGISTER – OFFSET 00h ..................................................................................60 13.2.2 DEVICE ID REGISTER – OFFSET 00h....................................................................................60 13.2.3 COMMAND REGISTER – OFFSET 04h ...................................................................................60 13.2.4 PRIMARY STATUS REGISTER – OFFSET 04h ......................................................................61 13.2.5 REVISION ID REGISTER – OFFSET 08h................................................................................62 13.2.6 CLASS CODE REGISTER – OFFSET 08h ................................................................................62 13.2.7 CACHE LINE REGISTER – OFFSET 0Ch ...............................................................................62 13.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch.....................................................62 13.2.9 HEADER TYPE REGISTER – OFFSET 0Ch ............................................................................62 13.2.10 PRIMARY BUS NUMBER REGISTER – OFFSET 18h .......................................................62 13.2.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................63 13.2.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................63 13.2.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ...........................................63 13.2.14 I/O BASE ADDRESS REGISTER – OFFSET 1Ch................................................................63 13.2.15 I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ..............................................................63 13.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch............................................................64 13.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h ....................................................64 13.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ...................................................65 13.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h....................65 13.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ..................65 13.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ...................................................................................................................................................65 13.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ...................................................................................................................................................66 13.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ...................................66 13.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ..................................66 13.2.25 CAPABILITY POINTER REGISTER – OFFSET 34h ..........................................................66 13.2.26 INTERRUPT LINE REGISTER – OFFSET 3Ch ..................................................................66 13.2.27 INTERRUPT PIN REGISTER – OFFSET 3Ch .....................................................................66 13.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................67 13.2.29 SUBSYSTEM VENDOR ID REGISTER – OFFSET 40h ......................................................68 13.2.30 SUBSYSTEM ID REGISTER – OFFSET 40h........................................................................68 13.2.31 DIAGNOSTIC/CHIP CONTROL REGISTER – OFFSET 44h .............................................68 13.2.32 ARBITER CONTROL REGISTER – OFFSET 44h ...............................................................70 13.2.33 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h ................................................70 13.2.34 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch ..71 13.2.35 P_SERR# EVENT DISABLE REGISTER – OFFSET 64h ...................................................71 13.2.36 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ..........................................72 13.2.37 P_SERR# STATUS REGISTER – OFFSET 68h....................................................................73 13.2.38 CLKRUN REGISTER – OFFSET 6Ch ...................................................................................74 13.2.39 PORT OPTION REGISTER – OFFSET 74h..........................................................................74 13.2.40 CAPABILITY ID REGISTER – OFFSET 80h .......................................................................76 13.2.41 NEXT ITEM POINTER REGISTER – OFFSET 80h ............................................................76 13.2.42 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ............................76 13.2.43 POWER MANAGEMENT DATA REGISTER – OFFSET 84h.............................................77 13.2.44 PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 88h ..........................77 13.2.45 SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 88h ....................77 13.2.46 CAPABILITY ID REGISTER – OFFSET 90h .......................................................................77 13.2.47 NEXT ITEM POINTER REGISTER – OFFSET 90h ............................................................77 13.2.48 HOT SWAP CAPABILITY STRUCTURE REGISTER – OFFSET 90h ...............................78 13.2.49 HOT SWAP SWITCH REGISTER – OFFSET 94h ...............................................................78 07-0067 |
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