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MPC8270VR Datasheet(PDF) 22 Page - Freescale Semiconductor, Inc |
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MPC8270VR Datasheet(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 83 page ![]() MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2 22 Freescale Semiconductor AC Electrical Characteristics NOTE Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. This table lists SIU input characteristics. This table lists SIU output characteristics. Table 13. AC Characteristics for SIU Inputs1 1 Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. Spec Number Characteristic Value (ns) Setup Hold Setup Hold 66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz sp11 sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/ TEA 6 5 3.5 0.5 0.5 0.5 sp12 sp10 Data bus in normal mode 5 4 3.5 0.5 0.5 0.5 sp13 sp10 Data bus in ECC and PARITY modes 7 5 3.5 0.5 0.5 0.5 sp13a sp10 Pipeline mode—Data bus (with or without ECC/PARITY) 5 4 2.5 0.5 0.5 0.5 sp14 sp10 DP pins 7 5 3.5 0.5 0.5 0.5 sp14a sp10 Pipeline mode—DP pins — 4 2.5 — 0.5 0.5 sp15 sp10 All other pins 5 4 3.5 0.5 0.5 0.5 Table 14. AC Characteristics for SIU Outputs1 1 Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. Spec Number Characteristic Value (ns) Max Min Maximum Delay Minimum Delay 66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz sp31 sp30 PSDVAL/TEA/TA 76 5.5 1 11 sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT 8 6.5 5.5 1 1 1 sp33a sp30 Data bus2 2 To achieve 1 ns of hold time at 66, 83, or 100 MHz, a minimum loading of 20 pF is required. 6.5 6.5 5.5 0.7 0.7 0.7 sp33b sp30 DP 6 5.5 5.5 1 1 1 sp34 sp30 Memory controller signals/ALE 6 5.5 5.5 1 1 1 sp35 sp30 All other signals 6 5.5 5.5 1 1 1 sp35a sp30 AP 7771 11 |
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