13

Errata

Implication:

Software cannot rely on these bits.

Workaround:

Refer to your Intel Representative for workaround details.

Status:

For the steppings effected, see the Summary Table of Changes.

14.

MCH transitions from Polling.Active prematurely

Problem:

During a standard link training sequence, the MCH should remain in Polling.Active until TS1

ordered sets with link and lane set to PAD are received on all lanes that passed Receiver Detect.

Because the MCH does not explicitly check for PAD on the link and lane numbers, it is possible for

the MCH to transition from Polling.Active to Polling.Config when a downstream device is not

executing a standard link training sequence (i.e. when the downstream device is actually in

recovery or reset).

Implication:

This early transition to Polling.Config may result in a degraded link width (e.g. a x4 port may train

as x1), but the link will train.

Workaround:

None required.

Status:

For the steppings effected, see the Summary Table of Changes.

15.

Non-fatal completion timeout errors observed on PCI Express devices

Problem:

When PCI configuration accesses are made on secondary buses to MCH PCI Express bridges

(Device 2-3, Function 0), non-fatal completion timeout errors (EXP_UNCERRSTS, Device 2-3,

Function 0, Offset 104h bit 14) may be observed in the MCH. This condition also applies to PCI

configuration accesses on any downstream device that is in the hot reset state or is disabled.

Implication:

The system may escalate non-fatal PCI Express completion timeout errors inadvertently.

Workaround:

There are two viable workarounds:

1. Mask the completion timeout errors on MCH PCI Express bridge devices with unpopulated

slots as identified by the Present Detect State bit (EXP_SLTSTS, Device 2-3, Function 0,

Offset 7Eh bit 6) in the PCI Express Slot Status register. If a device is present but disabled or in

the hot reset state then the L ink Active bit (VS_STS1, Device 2-3, Function 0, Offset 47h bit

1) should be verified for link status.

2. Construct a completion timeout handler to clear the error and return if the Present Detect State

bit and the Link Active bit are clear.

Status:

For the steppings effected, see the Summary Table of Changes.

16.

MCH fails to train when non-TS1/TS2 training sequences are received

Problem:

During the PCI Express training sequence, if a broken endpoint or a good endpoint on a broken

board has correct receiver termination on any lane and transmits signals on that lane that can be

seen at the MCH and are not valid TS1/TS2 training sequences, the MCH will fail to train that link

at all.

Implication:

The PCI Express specification intends that, if some lanes are transmitting bogus data instead of

valid training sequences, those lanes should be treated as broken, and the link should fail down to

an acceptable width (such as x1). If lane 0 were failing in this manner, the link would fail to train

per the PCI Express specification. If a higher-numbered lane were failing in this manner, the PCI

DRAM_SCRB_ADD

D0:F1:A8-ABh

DRAM_RETR_ADD

D0:F1:AC-AFh

DRAM_SEC2_ADD

D0:F1:C8-CBh

Register

Device:Function:Offset