TMP108

SBOS663 – APRIL 2013

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TIMING DIAGRAMS

The TMP108 is two-wire and SMBus compatible. Figure 12 to Figure 15 describe the various operations on the

TMP108. Parameters for Figure 12 are defined in Table 12. Bus definitions are:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high defines a

start condition. Each data transfer is initiated with a start condition.

Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a

stop condition. Each data transfer is terminated with a repeated start or stop condition.

Data Transfer: The number of data bytes transferred between a start and a stop condition is not limited, and is

determined by the master device. The receiver acknowledges the transfer of data. It is also possible to use the

TMP108 for single-byte updates. To update only the MS byte, terminate communication by issuing a start or stop

condition on the bus.

Acknowledge: Each receiving device, when addressed, must generate an acknowledge bit. A device that

acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable

low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account.

When a master receives data, the termination of the data transfer can be signaled by the master generating a

not-acknowledge ('1') on the last byte transmitted by the slave.

Table 12. Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

SCL operating frequency, V+

≥ 1.8 V

0.001

0.4

0.001

3.4

MHz

SCL operating frequency, V+ < 1.8 V

0.001

0.4

0.001

2.5

MHz

Bus free time between stop and start conditions, V+

1300

160

ns

≥ 1.8 V

Bus free time between stop and start conditions, V+

1300

260

ns

< 1.8 V

Hold time after repeated start condition.

600

160

ns

After this period, the first clock is generated.

Repeated start condition setup time

600

160

ns

Stop condition setup time

600

160

ns

Data hold time, V+

≥ 1.8 V

0

900

0

70

ns

Data hold time, V+ < 1.8 V

0

900

0

130

ns

Data setup time, V+

≥ 1.8 V

100

10

ns

Data setup time, V+ < 1.8 V

100

50

ns

SCL clock low period, V+

≥ 1.8 V

1300

160

ns

SCL clock low period, V+ < 1.8 V

1300

260

ns

SCL clock high period

600

60

ns

Data rise/fall time

300

80

ns

Clock rise/fall time

300

40

ns

Clock/data rise time for SCLK

≤ 100 kHz

1000

ns

14

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