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ST7LITE25F2 Datasheet(PDF) 143 Page - STMicroelectronics |
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ST7LITE25F2 Datasheet(HTML) 143 Page - STMicroelectronics |
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143 / 166 page  ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Doc ID 8349 Rev 5 143/166 Figure 88. SPI Master Timing Diagram(1) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 13.11 10-Bit ADC characteristics SS INPUT CPHA=0 MOSI OUTPUT MISO INPUT CPHA=0 CPHA=1 CPHA=1 tc(SCK) tw(SCKH) tw(SCKL) th(MI) tsu(MI) tv(MO) th(MO) MSB IN MSB OUT BIT6 IN BIT6 OUT LSB OUT LSB IN (2) (2) CPOL=0 CPOL=1 CPOL=0 CPOL=1 tr(SCK) tf(SCK) Table 84. 10-Bit ADC characteristics(1) 1. Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Min Typ(2) 2. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guidelines and are not tested. Max Unit fADC ADC clock frequency −− − 4MHz VAIN Conversion voltage range(3) 3. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS. − VSSA − VDDA V RAIN External input resistor −− − 10(4) 4. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k Ω). Data based on characterization results, not tested in production. k Ω CADC Internal sample and hold capacitor −− 6 − pF tSTAB Stabilization time after ADC enable fCPU=8MHz, fADC=4MHz 0(5) μs tADC Conversion time (Sample+Hold) 3.5 - Sample capacitor loading time - Hold conversion time 4 10 1/fADC IADC Analog Part −− − 1 mA Digital Part −− − 0.2 |
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