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SI-50170 Datasheet(PDF) 13 Page - Micrel Semiconductor

Part # SI-50170
Description  10Base-T/100Base-TX Physical Layer Transceiver
PDF  54 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SI-50170 Datasheet(HTML) 13 Page - Micrel Semiconductor

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Micrel, Inc.
KSZ8041NL/RNL
September 2010
13
M9999-090910-1.4
Pin Description – KSZ8041NL (Continued)
Pin Number
Pin Name
Type
(1)
Pin Function
31
LED1 /
SPEED
Ipu/O
LED Output:
Programmable LED1 Output /
Config Mode:
Latched as SPEED (register 0h, bit 13) during power-up / reset.
See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows.
LED mode = [00]
Speed
Pin State
LED Definition
10BT
H
OFF
100BT
L
ON
LED mode = [01]
Activity
Pin State
LED Definition
No Activity
H
OFF
Activity
Toggle
Blinking
LED mode = [10]
Reserved
LED mode = [11]
Reserved
32
RST#
I
Chip Reset (active low)
PADDLE
GND
Gnd
Ground
Notes:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipd = Input with internal pull-down (40K +/-30%).
Ipu = Input with internal pull-up (40K +/-30%).
Opu = Output with internal pull-up (40K +/-30%).
Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the
MII. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of
recovered data are sent from the PHY.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through
the MII. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are
received by the PHY from the MAC.



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