M68HC08 datasheet(206/332 Pages) FREESCALE

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Universal Serial Bus Module (USB)

Technical Data

MC68HC908JB16 — Rev. 1.1

206

Universal Serial Bus Module (USB)

Freescale Semiconductor

11.9.1.4 Transmit Endpoint 2

For an IN transaction directed at endpoint 2, the USB module will

generate an interrupt by setting the TXD2F in the UIR1 register.

11.9.1.5 Receive Endpoint 2

For an OUT transaction directed at endpoint 2, the USB module will

generate an interrupt by setting the RXD2F in the UIR1 register.

11.9.2 Resume Interrupt

The USB module will generate a CPU interrupt if low-speed bus activity

is detected after entering the suspend state. A transition of the USB data

lines to the non-idle state (K state) while in the suspend mode will set the

RESUMF flag in the UIR1 register. There is no interrupt enable bit for this

interrupt source and an interrupt will be executed if the I-bit in the CCR

is cleared. A resume interrupt can only occur while the MCU is in the

suspend mode.

11.9.3 End-of-Packet Interrupt

The USB module can generate a USB interrupt upon detection of an

end-of-packet signal for low-speed devices. Upon detection of an end-

of-packet signal, the USB module sets the EOPF bit and will generate a

CPU interrupt if the EOPIE bit in the UIR0 register is set.

M68HC08 Datasheet(PDF) 206 Page - Freescale Semiconductor, Inc