CAT93C46 datasheet(3/16 Pages) ONSEMI

3 / 16 page

CAT93C46

http://onsemi.com

Table 4. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (REV P)

(VCC = +1.8 V to +5.5 V, TA = −40°C to +125°C, VCC = +1.65 V to +5.5 V, TA = −20°C to +85°C unless otherwise specified.)

Symbol

Parameter

Test Conditions

Min

Max

Units

ICC1

Supply Current (Write)

Write, VCC = 5.0 V

ICC2

Supply Current (Read)

Read, DO open, fSK = 2 MHz, VCC = 5.0 V

500

ISB1

Standby Current

(x8 Mode)

VIN = GND or VCC

CS = GND, ORG = GND

TA = −40°C to +85°C

TA = −40°C to +125°C

ISB2

Standby Current

(x16 Mode)

VIN = GND or VCC

CS = GND,

ORG = Float or VCC

TA = −40°C to +85°C

TA = −40°C to +125°C

ILI

Input Leakage Current

VIN = GND to VCC

TA = −40°C to +85°C

TA = −40°C to +125°C

ILO

Output Leakage

Current

VOUT = GND to VCC

CS = GND

TA = −40°C to +85°C

TA = −40°C to +125°C

VIL1

Input Low Voltage

4.5 V ≤ VCC < 5.5 V

−0.1

0.8

VIH1

Input High Voltage

4.5 V ≤ VCC < 5.5 V

VCC + 1

VIL2

Input Low Voltage

1.8 V ≤ VCC < 4.5 V

VCC x 0.2

VIH2

Input High Voltage

1.8 V ≤ VCC < 4.5 V

VCC x 0.7

VCC + 1

VOL1

Output Low Voltage

4.5 V ≤ VCC < 5.5 V, IOL = 3 mA

0.4

VOH1

Output High Voltage

4.5 V ≤ VCC < 5.5 V, IOH = −400 mA

2.4

VOL2

Output Low Voltage

1.8 V ≤ VCC < 4.5 V, IOL = 1 mA

0.2

VOH2

Output High Voltage

1.8 V ≤ VCC < 4.5 V, IOH = −100 mA

VCC − 0.2

Table 5. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V)

Symbol

Test

Conditions

Min

Typ

Max

Units

COUT (Note 4)

Output Capacitance (DO)

VOUT = 0 V

CIN (Note 4)

Input Capacitance (CS, SK, DI, ORG)

VIN = 0 V

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

Table 6. A.C. CHARACTERISTICS − MATURE PRODUCT (Not Recommended for New Designs)

(VCC = +1.8 V to +5.5 V, TA = −40°C to +85°C, unless otherwise specified.) (Note 5)

Symbol

Parameter

Min Limit

Max Limit

Units

tCSS

CS Setup Time

tCSH

CS Hold Time

tDIS

DI Setup Time

100

tDIH

DI Hold Time

100

tPD1

Output Delay to 1

0.25

tPD0

Output Delay to 0

0.25

tHZ (Note 6)

Output Delay to High−Z

100

tEW

Program/Erase Pulse Width

tCSMIN

Minimum CS Low Time

0.25

tSKHI

Minimum SK High Time

0.25

tSKLOW

Minimum SK Low Time

0.25

tSV

Output Delay to Status Valid

0.25

SKMAX

Maximum Clock Frequency

2000

kHz

5. Test conditions according to “AC Test Conditions” table.

6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

CAT93C46 Datasheet(PDF) 3 Page - ON Semiconductor

CAT93C46 Datasheet(HTML) 3 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL