AD5313 datasheet(14/24 Pages) AD

14 / 24 page

AD5304/AD5314/AD5324

Data Sheet

Rev. H | Page 14 of 24

THEORY OF OPERATION

FUNCTIONAL DESCRIPTION

The AD5304/AD5314/AD5324 are quad, resistor-string DACs

fabricated on a CMOS process with resolutions of 8, 10, and 12

bits, respectively. Each contains four output buffer amplifiers and

is written to via a 3-wire serial interface. They operate from single

supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide

rail-to-rail output swing with a slew rate of 0.7 V/μs. The four

DACs share a single reference input pin. The devices have pro-

grammable power-down modes, in which all DACs can be turned

off completely with a high impedance output.

Digital-to-Analog

The architecture of one DAC channel consists of a resistor-string

DAC followed by an output buffer amplifier. The voltage at the

REFIN pin provides the reference voltage for the DAC. Figure 30

shows a block diagram of the DAC architecture. Since the input

coding to the DAC is straight binary, the ideal output voltage is

given by

REF

OUT





where

D = decimal equivalent of the binary code that is loaded to the

DAC register:

0–255 for AD5304 (8 bits)

0–1023 for AD5314 (10 bits)

0–4095 for AD5324 (12 bits)

N = DAC resolution.

REFIN

OUTPUT BUFFER

AMPLIFIER

RESISTOR

STRING

DAC

INPUT

VOUTA

Figure 30. DAC Channel Architecture

Resistor String

The resistor string section is shown in Figure 31. It is simply a

string of resistors, each of value R. The digital code loaded to the

DAC register determines at which node on the string the voltage

is tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is guaranteed

monotonic.

TO OUTPUT

AMPLIFIER

Figure 31. Resistor String

DAC Reference Inputs

There is a single reference input pin for the four DACs. The

reference input is not buffered. The user can have a reference

voltage as low as 0.25 V or as high as VDD because there is no

restriction due to the headroom or footroom requirements of

any reference amplifier. It is recommended to use a buffered

reference in the external circuit (for example, REF192). The

input impedance is typically 45 kΩ.

Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output, giving an output range of 0 V to VDD when

the reference is VDD. It is capable of driving a load of 2 kΩ to

GND or VDD, in parallel with 500 pF to GND or VDD. The source

and sink capabilities of the output amplifier can be seen in the

plot in Figure 15.

The slew rate is 0.7 V/μs with a half-scale settling time to

±0.5 LSB (at eight bits) of 6 μs.

POWER-ON RESET

The AD5304/AD5314/AD5324 are provided with a power-on reset

function, so that they power up in a defined state. The power-on

state uses normal operation and an output voltage set to 0 V.

Both input and DAC registers are filled with zeros and remain

so until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

SERIAL INTERFACE

The AD5304/AD5314/AD5324 are controlled over a versatile,

3-wire serial interface that operates at clock rates up to 30 MHz

and are compatible with SPI, QSPI, MICROWIRE, and DSP

interface standards.

AD5313 Datasheet(PDF) 14 Page - Analog Devices

AD5313 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL