AD5313 datasheet(15/24 Pages) AD

15 / 24 page

Data Sheet

AD5304/AD5314/AD5324

Rev. H | Page 15 of 24

BIT15

(MSB)

D6 D5 D4 D3

BIT0

(LSB)

PD LDAC

DATA BITS

Figure 32. AD5304 Input Shift Register Contents

BIT15

(MSB)

BIT0

(LSB)

D5 D4

PD LDAC

DATA BITS

Figure 33. AD5314 Input Shift Register Contents

BIT15

(MSB)

BIT0

(LSB)

D10

D11

D5 D4

PD LDAC

DATA BITS

Figure 34. AD5324 Input Shift Register Contents

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the

device as a 16-bit word under the control of a serial clock input,

SCLK. See Figure 2 for the timing diagram of this operation. The

16-bit word consists of four control bits followed by 8, 10, or 12

bits of DAC data, depending on the device type. Data is loaded

MSB first (Bit 15) and the first two bits determine whether the

data is for DAC A, DAC B, DAC C, or DAC D. Bit 13 and Bit 12

control the operating mode of the DAC. Bit 13 is PD, and deter-

mines whether the part is in normal or power-down mode. Bit 12 is

LDAC, and controls when DAC registers and outputs are updated.

Table 6. Address Bits

DAC Addressed

DAC A

DAC B

DAC C

DAC D

Address and Control Bits

0: All four DACs go into power-down mode, consuming

only 200 nA @ 5 V. The DAC outputs enter a high

impedance state.

1: Normal operation.

LDAC

0: All four DAC registers and, therefore, all DAC outputs

updated simultaneously on completion of the write

sequence.

1: Only addressed input register is updated. There is

no change in the content of the DAC registers.

The AD5324 uses all 12 bits of DAC data; the AD5314 uses 10 bits

and ignores the 2 LSB Bits. The AD5304 uses eight bits and ignores

the last four bits. The data format is straight binary, with all 0s

corresponding to 0 V output and all 1s corresponding to full-scale

output (VREF − 1 LSB).

The SYNC input is a level-triggered input that acts as a frame

synchronization signal and chip enable. Data can be transferred

into the device only while SYNC is low. To start the serial data

transfer, take SYNC low, observing the minimum SYNC to SCLK

falling edge setup time, t4. After SYNC goes low, serial data shifts

into the device’s input shift register on the falling edges of SCLK

for 16 clock pulses. Any data and clock pulses after the 16th falling

edge of SCLK are ignored because the SCLK and DIN input buffers

are powered down. No further serial data transfer occurs until

SYNC is taken high and low again.

SYNC can be taken high after the falling edge of the 16th SCLK

pulse, observing the minimum SCLK falling edge to SYNC

rising edge time, t7.

After the end of the serial data transfer, data automatically transfers

from the input shift register to the input register of the selected

DAC. If SYNC is taken high before the 16th falling edge of SCLK,

the data transfer is aborted and the DAC input registers are not

updated.

When data has been transferred into three of the DAC input

registers, all DAC registers and all DAC outputs are simultaneously

updated by setting LDAC low when writing to the remaining

DAC input register.

Low Power Serial Interface

To reduce the power consumption of the device even further, the

interface fully powers up only when the device is being written

to, that is, on the falling edge of SYNC. As soon as the 16-bit

control word has been written to the part, the SCLK and DIN

input buffers are powered down. They power up again only

following a falling edge of SYNC.

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