OP296 datasheet(42/88 Pages) AD

42 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 42 of 88

PULSE-WIDTH MODULATOR (PWM)

The PWM on the ADuC841/ADuC842/ADuC843 is a highly

flexible PWM offering programmable resolution and an input

clock, and can be configured for any one of six different modes

of operation. Two of these modes allow the PWM to be config-

ured as a ∑-∆ DAC with up to 16 bits of resolution. A block

diagram of the PWM is shown in Figure 47. Note the PWM

clock’s sources are different for the ADuC841, and are given in

Table 17.

CLOCK

SELECT

PROGRAMMABLE

DIVIDER

COMPARE

MODE

PWM0H/L

PWM1H/L

VCO

TO/EXTERNAL PWM CLOCK

fXTAL/15

fXTAL

P2.6

P2.7

16-BIT PWM COUNTER

Figure 47. PWM Block Diagram

The PWM uses five SFRs: the control SFR (PWMCON) and

four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L).

PWMCON, as described in the following sections, controls the

different modes of operation of the PWM as well as the PWM

clock frequency.

PWM0H/L and PWM1H/L are the data registers that deter-

mine the duty cycles of the PWM outputs. The output pins that

the PWM uses are determined by the CFG841/CFG842 register,

and can be either P2.6 and P2.7 or P3.4 and P3.3. In this section

of the data sheet, it is assumed that P2.6 and P2.7 are selected as

the PWM outputs.

To use the PWM user software, first write to PWMCON to

select the PWM mode of operation and the PWM input clock.

Writing to PWMCON also resets the PWM counter. In any of

the 16-bit modes of operation (Modes 1, 3, 4, 6), user software

should write to the PWM0L or PWM1L SFRs first. This value is

written to a hidden SFR. Writing to the PWM0H or PWM1H

SFRs updates both the PWMxH and the PWMxL SFRs but does

not change the outputs until the end of the PWM cycle in

progress. The values written to these 16-bit registers are then

used in the next PWM cycle.

PWMCON PWM

Control SFR

SFR Address

AEH

Power-On Default

00H

Bit Addressable

Table 17. PWMCON SFR Bit Designations

Bit No.

Name

Description

SNGL

Turns off PMW output at P2.6 or P3.4, leaving the port pin free for digital I/O.

MD2

PWM Mode Bits.

MD1

The MD2/1/0 bits choose the PWM mode as follows:

MD2

MD1

MD0

Mode

Mode 0: PWM Disabled

Mode 1: Single variable resolution PWM on P2.7 or P3.3

Mode 2: Twin 8-bit PWM

Mode 3: Twin 16-bit PWM

Mode 4: Dual NRZ 16-bit ∑-∆ DAC

Mode 5: Dual 8-bit PWM

Mode 6: Dual RZ 16-bit ∑-∆ DAC

MD0

Reserved

CDIV1

PWM Clock Divider.

Scale the clock source for the PWM counter as follows:

CDIV1

CDIV0

Description

PWM Counter = Selected Clock/1

PWM Counter = Selected Clock/4

PWM Counter = Selected Clock/16

CDIV0

PWM Counter = Selected Clock/64

CSEL1

PWM Clock Divider.

Select the clock source for the PWM as follows:

CSEL1

CSEL0

Description

PWM Clock = fXTAL/15, ADuC841 = fOCS/DIVIDE FACTOR /15 (see the CFG841 register)

PWM Clock = fXTAL, ADuC841 = fOCS/DIVIDE FACTOR (see the CFG841 register)

PWM Clock = External input at P3.4/T0

CSEL0

PWM Clock = fVCO = 16.777216 MHz, ADuC841 = fOSC

OP296 Datasheet(PDF) 42 Page - Analog Devices

OP296 Datasheet(HTML) 42 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL