OP296 datasheet(58/88 Pages) AD

58 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 58 of 88

In general-purpose I/O port mode, Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups

(Figure 60) and, in that state, can be used as inputs. As inputs,

Port 2 pins being pulled externally low source current because

of the internal pull-up resistors. Port 2 pins with 0s written to

them drive a logic low output voltage (VOL) and are capable of

sinking 1.6 mA.

P2.6 and P2.7 can also be used as PWM outputs. When they are

selected as the PWM outputs via the CFG841/CFG842 SFR, the

PWM outputs overwrite anything written to P2.6 or P2.7.

CONTROL

READ

LATCH

INTERNAL

BUS

WRITE

TO LATCH

READ

LATCH

DVDD

ADDR

P2.x

DVDD

INTERNAL

PULL-UP*

* SEE FOLLOWING FIGURE FOR

DETAILS OF INTERNAL PULL-UP

Figure 59. Port 2 Bit Latch and I/O Buffer

FROM

PORT

LATCH

2 CLK

DELAY

DVDD

Px.x

Figure 60. Internal Pull-Up Configuration

Port 3

Port 3 is a bidirectional port with internal pull-ups directly

controlled via the P3 SFR. Port 3 pins that have 1s written to

them are pulled high by the internal pull-ups and, in that state,

can be used as inputs. As inputs, Port 3 pins being pulled

externally low source current because of the internal pull-ups.

Port 3 pins with 0s written to them will drive a logic low output

voltage (VOL) and are capable of sinking 4 mA. Port 3 pins also

have various secondary functions as described in Table 26. The

alternate functions of Port 3 pins can be activated only if the

corresponding bit latch in the P3 SFR contains a 1. Otherwise,

the port pin is stuck at 0.

Table 26. Port 3 Alternate Pin Functions

Pin No.

Alternate Function

P3.0

RxD (UART Input Pin) (or Serial Data I/O in Mode 0)

P3.1

TxD (UART Output Pin) (or Serial Clock Output in Mode 0)

P3.2

INT0 (External Interrupt 0)

P3.3

INT1 (External Interrupt 1)/PWM 1/MISO

P3.4

T0 (Timer/Counter 0 External Input)

PWM External Clock/PWM 0

P3.5

T1 (Timer/Counter 1 External Input)

P3.6

WR (External Data Memory Write Strobe)

P3.7

RD (External Data Memory Read Strobe)

P3.3 and P3.4 can also be used as PWM outputs. When they are

selected as the PWM outputs via the CFG841/CFG842 SFR, the

PWM outputs overwrite anything written to P3.4 or P3.3.

READ

LATCH

INTERNAL

BUS

WRITE

TO LATCH

READ

LATCH

DVDD

P3.x

INTERNAL

PULL-UP*

* SEE PREVIOUS FIGURE

FOR DETAILS OF

INTERNAL PULL-UP

ALTERNATE

OUTPUT

FUNCTION

ALTERNATE

INPUT

FUNCTION

Figure 61. Port 3 Bit Latch and I/O Buffer

Additional Digital I/O

In addition to the port pins, the dedicated SPI/I2C pins (SCLOCK

and SDATA/MOSI) also feature both input and output func-

tions. Their equivalent I/O architectures are illustrated in

Figure 62 and Figure 64, respectively, for SPI operation and in

Figure 63 and Figure 65 for I2C operation. Notice that in I2C

mode (SPE = 0), the strong pull-up FET (Q1) is disabled,

leaving only a weak pull-up (Q2) present. By contrast, in SPI

mode (SPE = 1) the strong pull-up FET (Q1) is controlled

directly by SPI hardware, giving the pin push-pull capability.

In I2C mode (SPE = 0), two pull-down FETs (Q3 and Q4)

operate in parallel to provide an extra 60% or 70% of current

sinking capability. In SPI mode (SPE = 1), however, only one of

the pull-down FETs (Q3) operates on each pin, resulting in sink

capabilities identical to that of Port 0 and Port 2 pins. On the

input path of SCLOCK, notice that a Schmitt trigger conditions

the signal going to the SPI hardware to prevent false triggers

(double triggers) on slow incoming edges. For incoming signals

from the SCLOCK and SDATA pins going to I2C hardware, a

filter conditions the signals to reject glitches of up to 50 ns in

duration.

Notice also that direct access to the SCLOCK and SDATA/

MOSI pins is afforded through the SFR interface in I2C master

mode. Therefore, if you are not using the SPI or I2C functions,

you can use these two pins to give additional high current

digital outputs.

SCHMITT

TRIGGER

Q2 (OFF)

DVDD

Q4 (OFF)

SCLOCK

SPE = 1 (SPI ENABLE)

HARDWARE SPI

(MASTER/SLAVE)

Figure 62. SCLOCK Pin I/O Functional Equivalent in SPI Mode

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