IRF7401 datasheet(19/22 Pages) AD

19 / 22 page

REV.

ADN8830

–19–

Power Supply Ripple

Minimizing ripple on the power supply voltage can be an impor-

tant consideration, particularly in signal source laser applications.

If the laser diode is operated from the same supply rail as the TEC

controller, ripple on the supply voltage could cause inadvertent

modulation of the laser frequency. As most laser diodes are driven

from a 5 V supply, it is recommended the ADN8830 be operated

from a separate 3.3 V regulated supply unless higher TEC voltages

are required. Operation from 3.3 V also improves efficiency, thus

minimizing power dissipation.

The power supply ripple is primarily a function of the supply by-

pass capacitance, also called bulk capacitance, and the inductor

ripple current. Similar to the L-C filter at the PWM amplifier

output, using more capacitance with low equivalent series resis-

tance (ESR) will lower the supply ripple. A larger inductor value

will reduce the inductor ripple current, but this may not be

practical in the application. A recommended approach is to use a

standard electrolytic capacitor in parallel with a low ESR capacitor.

A surface-mount 220

μF electrolytic in parallel with a 22 μF poly-

mer aluminum low ESR capacitor can occupy an approximate total

board area of only 0.94 square inches or 61 square millimeters.

Using these capacitors along with a 4.7

μH inductor can yield a

supply ripple of less than 5 mV.

High frequency transient spikes may appear on the supply voltage

as well. This is due to the fast switching times on the PWM transis-

tors and the sharp edges of their gate voltages. Although these

transient spikes can reach several tens of millivolts at their peak,

they typically last for less than 20 ns and have a resonance greater

than 100 MHz. Additional bulk capacitance will not appreciably

affect the level of these spikes as such capacitance is not reactive at

these frequencies. Adding 0.01

μF ceramic capacitors on the sup-

ply line near the PWM PMOS transistor can reduce this switching

noise. Inserting an RF inductor with a High-Q around 100 MHz in

series with PVDD will also block this noise from traveling back to

the power supply.

Setting Maximum Output Current and Short-Circuit

Protection

Although the maximum output voltage can be programmed

through VLIM to protect the TEC from overvoltage damage,

the user may wish to protect the ADN8830 circuit from a possible

short circuit at the output. Such a short could quickly damage the

external FETs or even the power supply since they would attempt

to drive excessive current. Figure 20 shows a simple modification

that will protect the system from an output short circuit.

1 F

DENOTES

PGND

MA116CT-ND

EQUIVALENT

AVDD

FDV304P

OR EQUIVALENT

PVDD

10m

100k

PVDD

DENOTES

AGND

FETS

AND

DECOUPLING

CAPS

AD8601

Figure 20. Implementing Output Short-Circuit Protection

A 10 m

Ω resistor placed in series with the PVDD supply line creates a

voltage drop proportional to the absolute value of the output current.

The AD8601 is a CMOS amplifier that is configured as a com-

parator. As long as the voltage at its inverting input (VS) exceeds

the voltage set by the resistor divider at the noninverting input (VX),

the gate of Q1 will remain at ground. This leaves Q1 on, effectively

connecting D1 to the positive rail and leaving the voltage on C1 at

VDD. Should enough current flow through RS to drop VS below VX,

Q1 will turn off and C1 will discharge through R2 down to a logic

low to activate the ADN8830 shutdown. Once VS returns to a

voltage greater than VX, Q1 will turn back on and C1 will charge

back to VDD through R1. The shutdown and reactivation time

constants are approximately

=×

(42)

The shutdown time constant should be a minimum of 10 clock

cycles to ensure high current switching transients do not trigger a

false activation. If powered from 5 V, the circuit shown will shut

down the ADN8830 should PVDD deliver over 5 A for more than

1 ms. After shutdown, the circuit will reactivate the ADN8830 in

about 1 second.

The voltage drop across RS is found as

IR R

OUT

(43)

where RL is the load resistance or resistance of the TEC and

the efficiency of the system. An estimate of efficiency can be calculated

either from the Calculating Power Dissipation and Efficiency section

or from Figures 16 and 17. A reasonable approximation is

0.85. Although the exact resistance of a TEC varies with tempera-

ture, an estimation can be made by dividing the maximum voltage

rating of the TEC by its maximum current rating.

In addition to providing protection against a short at the output,

this circuit will also protect the FETs against shoot-through current.

Shoot-through will not occur when using the recommended

transistors and additional capacitance shown in Tables V and VI.

However, if different transistors are used where their shoot-

through potential is unknown, implementing the short-circuit

protection circuit will unconditionally protect these transistors.

To set a maximum output current limit, use the circuit in Figure

21. This circuit can share the 10 m

Ω power supply shunt resistor

as the short-circuit protection circuit to sense the output current.

In normal operation Q1 is on, pulling the ADN8830 VLIM pin

down to the voltage set by VLIMIT. This sets the maximum out-

put voltage limit as described in the Setting the Maximum TEC

Voltage and Current section.

VLIM

1.47k

DENOTES

PGND

AVDD

FDV301N

EQUIVALENT

PVDD

10m

100k

178

PVDD

DENOTES

AGND

VSY

AD8605

VLIMIT

(0V TO 1.5V)

3.48k

1nF

FETS

AND

DECOUPLING

CAPS

Figure 21. Setting a Maximum Output Current Limit

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