IP1827 datasheet(18/39 Pages) IRF

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iP1827

Highly Integrated 25A Single‐input Voltage,

Synchronous Buck Regulator

March 5, 2012 | V1.4

97599

MINIMUM ON TIME CONSIDERATIONS

The minimum ON time is the shortest amount of time for

which the Control FET may be reliably turned on, and this

depends on the internal timing delays. For the iP1827,

the minimum on‐time is specified as 50 ns maximum.

Any design or application using the iP1827 must require a

pulse width that is at least equal to this minimum on‐time

and preferably higher than 100 ns. This is necessary for the

circuit to operate without jitter and pulse‐skipping, which

can cause high inductor current ripple and high output

voltage ripple.

MAXIMUM DUTY RATIO CONSIDERATIONS

For the iP1827, the upper limit on the operating duty ratio

is set by the duration of the PWMSet pulse or by the 200

ns fixed off‐time, whichever is higher. Since the PWMSet

pulse has a 25% duty cycle, this limits the maximum duty

ratio at which the iP1827 can operate, to 75%. At switching

frequencies above 1.25 MHz, however, the maximum duty

ratio is set by the 200 ns fixed off‐time. Thus, at switching

frequencies above 1.25 MHz, higher the switching

frequency, the lower is the maximum duty ratio at which

the iP1827 can operate. Figure 13 shows a plot of the

maximum duty ratio v/s the switching frequency, with 200

ns off‐time.

66%

67%

68%

69%

70%

71%

72%

73%

74%

75%

76%

250 350 450 550 650 750 850 950 1050 1150 1250 1350 1450 1550 1650

Switching Frequency (kHz)

Figure 13: Maximum duty cycle v/s switching frequency.

TRAILING EDGE PULSE WIDTH MODULATION

WITH RAMP‐SLOPE MODULATION

The iP1827 employs trailing edge Pulse width modulation.

However, unlike conventional trailing edge modulators,

which compare the PWM ramp with the output of the

error amplifier or the Comp voltage, in the modulation

scheme used in the iP1827, the slope of the PWM ramp

is modulated by the Comp voltage and this modulated

ramp is then compared to a fixed reference voltage.

The advantage of this scheme is that comparison always

takes place at a fixed reference irrespective of the duty

cycle of operation. Conventional modulators suffer from

increased noise susceptibility at the lower duty cycles,

since the comparison takes place at the Comp voltage level

which is close to the bottom of the PWM ramp for low

duty cycle operation.

Figure 14 shows theoretical waveforms for the PWM ramp

and the PWM output in response to a changing Comp

voltage. Figure 15 shows the variation of the modulator

gain (Fm) with the duty cycle (D).

Figure 14: Theoretical waveforms for the new PWM scheme

Modulator Gain = -2E-05D

2 + 0.0156D + 0.4168

0.2

0.4

0.6

0.8

1.2

1.4

10152025303540

455055

D(%)

Figure 15: Modulator gain (Fm) v/s Duty Ratio (D%)

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