59PR9875N datasheet(22/49 Pages) IRF

22 / 49 page

IR3448

www.irf.com

August 01, 2013

threshold

OVP(trip)

and

VPG_high(lower)

respectively. PGood signal is high whenever Vsns

voltage is within the PGood comparator window

thresholds. Hysteresis has been applied to the lower

threshold, PGood signal goes low when Vsns drops

below VPG_low(lower) instead of VPG_high(lower).

The PGood pin is open drain and it needs to be

externally pulled high. High state indicates that output

is in regulation. Figure 19 show the timing diagram of

the PGood signal. Vsns signal is also used by OVP

comparator

for

detecting

output

over

voltage

condition. PGood signal is low when Enable is low.

Figure 19: PGood Timing Diagram

OVER-VOLTAGE PROTECTION (OVP)

Over-voltage protection in IR3448 is achieved by

comparing sense pin voltage Vsns to a pre-set

threshold. When Vsns exceeds the over voltage

threshold, an over voltage trip signal asserts after 2.5

uS (typ.) delay. The high side drive signal HDrv is

latched off immediately and PGood flags are set low.

The low side drive signal is kept on until the Vsns

voltage drops below the threshold.

HDrv remains

latched off until a reset is performed by cycling VCC.

OVP is active when enable is high or low.

Vsns voltage is set by the voltage divider connected to

the output and it can be programmed externally.

Figure 20 shows the timing diagram for OVP.

Figure 20: Timing Diagram for OVP in non-tracking

mode

BODY BRAKING

The Body Braking feature of the IR3448 allows

improved transient response for step-down load

transients. A severe step-down load transient would

cause an overshoot in the output voltage and drive the

Comp pin voltage down until control saturation occurs

demanding 0% duty cycle and the PWM input to the

Control FET driver is kept OFF. When the first such

skipped pulse occurs, the IR3448 enters Body Braking

mode, wherein the Sync FET also turned OFF. The

inductor current then decays by freewheeling through

the body diode of the Sync FET. Thus, with Body

Braking, the forward voltage drop of the body diode

provides and additional voltage to discharge the

inductor current faster to the light load value as shown

in equation (3) and equation (4) below:







, with body braking

(3)





, without body braking

(4)

= Inductor current

= Forward voltage drop of the body diode of

the Sync FET.

= output voltage

= Inductor value

The Body Braking mechanism is kept OFF during pre-

bias operation. Also, in the event of an extremely

severe load step-down transient causing OVP, the

59PR9875N Datasheet(PDF) 22 Page - International Rectifier

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