59PR9875N datasheet(16/49 Pages) IRF

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IR3448

www.irf.com

August 01, 2013

THEORY OF OPERATION

DESCRIPTION

The IR3448 uses a PWM voltage mode control

scheme with external compensation to provide good

noise immunity and maximum flexibility in selecting

inductor values and capacitor types.

The switching frequency is programmable from

300kHz to 1.5MHz and provides the capability of

optimizing the design in terms of size and

performance.

IR3448 provides precisely regulated output voltage

programmed via two external resistors from 0.6V to

0.86*PVin.

The IR3448 operates with an internal bias supply

(LDO) which is connected to the VCC pin. This allows

operation with single supply. The bias voltage is

variable according to load condition. If the output load

current is less than half of the peak-to-peak inductor

current, a lower bias voltage, 4.4V, is used as the

internal gate drive voltage; otherwise, a higher

voltage, 6.8V, is used.

This feature helps the converter to reduce power

losses. The device can also be operated with an

external supply from 4.5V to 7.5V, allowing an

extended operating input voltage (PVin) range from

1.0V to 21V. For using the internal LDO supply, the

Vin pin should be connected to PVin pin. If an external

supply is used, it should be connected to VCC pin and

the Vin pin should be shorted to VCC pin.

The device utilizes the on-resistance of the low side

MOSFET (synchronous Mosfet) as current sense

element. This method enhances the converter’s

efficiency and reduces cost by eliminating the need for

external current sense resistor.

IR3448 includes two low Rds(on) MOSFETs using IR’s

HEXFET technology. These are specifically designed

for high efficiency applications.

UNDER-VOLTAGE LOCKOUT AND POR

The under-voltage lockout circuit monitors the voltage

of VCC pin and the Enable input. It assures that the

MOSFET driver outputs remain in the off state

whenever either of these two signals drops below the

set thresholds. Normal operation resumes once VCC

and Enable rise above their thresholds.

The POR (Power On Ready) signal is generated when

all these signals reach the valid logic level (see

system block diagram). When the POR is asserted the

soft start sequence starts (see soft start section).

ENABLE

The Enable features another level of flexibility for

startup. The Enable has precise threshold which is

internally

monitored

Under-Voltage

Lockout

(UVLO) circuit. Therefore, the IR3448 will turn on only

when the voltage at the Enable pin exceeds this

threshold, typically, 1.2V.

If the input to the Enable pin is derived from the bus

voltage by a suitably programmed resistive divider, it

can be ensured that the IR3448 does not turn on until

the bus voltage reaches the desired level Figure 4.

Only after the bus voltage reaches or exceeds this

level and voltage at the Enable pin exceeds its

threshold, IR3448 will be enabled. Therefore, in

addition to being a logic input pin to enable the

IR3448, the Enable feature, with its precise threshold,

also allows the user to implement an Under-Voltage

Lockout for the bus voltage (PVin). It can help prevent

the IR3448 from regulating at low PVin voltages that

can cause excessive input current.

Figure 4: Normal Start up, device turns on when the

bus voltage reaches 10.2V

A resistor divider is used at EN pin from PVin to turn

on the device at 10.2V.

59PR9875N Datasheet(PDF) 16 Page - International Rectifier

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