CN-0232

Circuit Note

Rev. 0 | Page 2 of 6

Devices with integrated PLLs and VCOs may have feed through

from the digital PLL circuitry to the VCO, leading to higher

spurious levels due to the close proximity of the PLL circuitry

to the VCO.

The circuit shown in Figure 1 uses the ADF4350, a fully integrated

fractional-N PLL and VCO that can generate frequencies from

137.5 MHz to 4400 MHz, together with the ADF4153 PLL.

In addition to improvements in spurious performance,

another possible advantage of using an external PLL is the

possibility of increased frequency resolution. For example,

if the ADF4157 PLL is selected in place of the ADF4153, the

frequency resolution of the PLL can be as fine as 0.7 Hz.

CIRCUIT DESCRIPTION

The ADF4350 is a wideband PLL and VCO consisting of

three separate multiband VCOs. Each VCO covers a range of

approximately 700 MHz (with some overlap between the

frequencies of the VCO). This permits a fundamental VCO

frequency range of between 2.2 GHz to 4.4 GHz. Frequencies

lower than 2.2 GHz can be generated using internal dividers

within the ADF4350.

For most applications, the internal PLL of the ADF4350 is used to

lock the VCO. In addition to locking the PLL, the PLL circuitry

performs an additional vital function of VCO band select, using

the internal reference (R) and feedback (N) counters of the internal

PLL to compare the VCO output with the reference input.

For frequency generation, the internal PLL must be enabled and

the desired frequency must be programmed. Then, once sufficient

time has elapsed for band select, the internal PLL can be disabled,

and, finally, the external PLL can be enabled. The external PLL

compares the reference frequency and the VCO output frequency

to generate a stable dc voltage to lock the PLL.

using the ADF4350 internal PLL and VCO with the ADF4153 PLL

disabled. Note the presence of PFD spurs at 13 MHz and 26 MHz.

ADF4350 internal PLL circuit disabled and the external ADF4153

PLL active. In this mode, the charge pump output of the ADF4153

frequency.

In making a comparison between Figure 2 and Figure 3, the spurs

due to the phase frequency detector (PFD) frequency, at 13 MHz

and 26 MHz, in Figure 2 have disappeared into the noise floor

in Figure 3.

COMMON VARIATIONS

Different PLLs can be selected. The fractional-N PLL in both the

ADF4350 and ADF4153 has a minimum frequency resolution

of PFD/4095. If finer resolution is required, the ADF4157

providing an ultrafine resolution of <1 Hz.

For applications requiring simpler software programmability,

the ADF4150 PLL is software compatible with the ADF4350,

easing the software programming sequence.