Circuit Note

CN-0248

Circuits from the Lab™ reference circuits are engineered and

tested for quick and easysystemintegrationto helpsolve today’s

analog, mixed-signal, and RF design challenges. For more

informationand/orsupport,visitwww.analog.com/CN0248.

Devices Connected/Referenced

ADRF6510

30 MHz Dual Programmable Filters and

Variable Gain Amplifiers

ADL5387

50 MHz to 2 GHz Quadrature

Demodulator

ADL5336

LF to 1 GHz VGA with 48 dB Gain Control

Range and Programmable RMS Detectors

An IQ Demodulator-Based IF-to-Baseband Receiver with IF and Baseband Variable

Gain and Programmable Baseband Filtering

Rev. 0

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EVALUATION AND DESIGN SUPPORT

Circuit Evaluation Boards

ADRF6510 Evaluation Board (ADRF6510-EVALZ)

ADL5387 Evaluation Board (ADL5387-EVALZ)

ADL5336 Evaluation Board (ADL5336-EVALZ)

AD8130 Evaluation Board (AD8130-EBZ) two required

Design and Integration Files

Schematics, Layout Files, Bill of Materials

CIRCUIT FUNCTION AND BENEFITS

This circuit is a flexible, frequency agile IF-to-baseband receiver.

Variable gain at both IF and baseband is used to adjust the signal

level. The ADRF6510 baseband ADC driver also includes a

programmable low-pass filter that eliminates out-of-channel

blockers and noise.

The bandwidth of this filter can be dynamically adjusted as the

bandwidth of the input signal changes. This ensures that the available

dynamic range of the ADC that this circuit drives is fully used.

The core of the circuit is an IQ demodulator. The 2×LO based

phase-splitting architecture of the ADL5387 allows for operation

over a wide frequency range. Precise quadrature balance and

low output dc offsets ensure that there is minimal degradation

of the error vector magnitude (EVM).

The interfaces between all of the components in this circuit are

fully differential. Where dc coupling is required between stages,

the bias levels of the adjacent stages are compatible with each other.

ADRF6510

I

Q

RF

DIV BY 2

ADL5387

2xLO

0°

90°

ADF4350

ADL5336

AD9248

BITS

BITS

VCO

CORE

Figure 1. Direct Conversion Receiver Simplified Schematic (All Connections and Decoupling Not Shown)