CN-0294

Circuit Note

Rev. 0 | Page 2 of 5

Modern digital systems often require many high quality clocks

at logic levels that are different from the logic level of the clock

source. Extra buffering may be required to guarantee accurate

distribution to other circuit components without loss of integrity.

The interface between the ADF4351clock source ADCLK948

clock fanout buffer is described, and measurements show that the

additive jitter associated with the clock fanout buffer is 75 fs rms.

CIRCUIT DESCRIPTION

The ADF4351 is a wideband PLL and VCO consisting of

three separate multiband VCOs. Each VCO covers a range

of approximately 700 MHz (with some overlap between the

frequencies of the VCO). This permits a fundamental VCO

frequency range of between 2.2 GHz to 4.4 GHz. Frequencies

lower than 2.2 GHz can be generated using internal dividers

within the ADF4351.

For clock generation, the ADF4351 PLL and VCO must be

enabled, and the desired output frequency must be programmed.

The output frequency of the ADF4351 is available at the open-

inductor (or resistor), plus a dc blocking capacitor.

The ADCLK948 is a SiGe low jitter clock fanout buffer that is

ideally suited for use with the ADF4351, because its maximum

input frequency (4.5 GHz) is just above that of the ADF4351

(4.4 GHz). Broadband rms additive jitter is 75 fs.

It is necessary to add a dc common-mode bias level of 1.65 V to

the CLK inputs of the ADCLK948 to mimic LVPECL logic levels.

This is accomplished by the use of a resistor bias network.

Omission of the dc bias circuit results in degraded signal

integrity at the ADCLK948 outputs.

COMMON VARIATIONS

Other possible synthesizers with integrated VCOs are the

ADF4350 fractional N (137 MHz to 4400 MHz) and the

ADF4360 integer N series.

Other possible clock fanout buffers in the same family as

the ADCLK948 are the ADCLK946 (6 LVPECL outputs),

ADCLK950 (10 LVPECL outputs), and the ADCLK954

(12 LVPECL outputs).

CIRCUIT EVALUATION AND TEST

The circuit is evaluated using the EVAL-ADF4351EB1Z board

for a clock source, with some minor modifications. The EVAL-

ADF4351EB1Z board uses the standard ADF4351 programming

software contained on the CD that accompanies the evaluation

board. The ADCLK948/PCBZ is also required and can be used

out of the box without modification.

Equipment Needed

The following equipment is needed:

•

The EVAL-ADF4351EB1Z evaluation board kit with

programming software

•

The ADCLK948PCBZ evaluation board

•

A 3.3 V power supply

•

Two cables to connect the 3.3 V supply to the

ADCLK948PCBZ

•

Two short equal length SMA coaxial cables

•

A high speed oscilloscope (2 GHz bandwidth) or an

equivalent

•

The R&S FSUP26 spectrum analyzer or an equivalent

•

A PC with Windows® XP, Windows, Vista (32-bit), or

Windows 7 (32-bit)

pins of the ADCLK948PCBZ.

Functional Block Diagram

For this experiment, the ADCLK948PCBZ and the EVAL-

ADF4351EB1Z are used. The boards are connected via a SMA

cable to the ADCLK948PCBZ, as shown in Figure 1.

HIGH-SPEED

OSCILLOSCOPE

R&S RTO1024

POWER

SUPPLY

RFOUTA+

RFOUTA−

PC

USB

COM

3.3V

ADF4351

EVALUATION BOARD

(EVAL-ADF4351EB1Z)

T7

ADCLK948/PCBZ

EVALUATION BOARD

J4

J2

CLK0

CLK0

OUT2

OUT2

Figure 2. ADF4351 Logic Level Measurement Setup

Getting Started

The UG-435 user guide details the installation and use of the

EVAL-ADF4351EB1Z evaluation software. UG-435 also

contains board setup instructions and the board schematic,

layout, and bill of materials. Necessary modifications to the board

are the insertion of 100 Ω resistors after the dc blocking capacitor.

The resistors are connected to 3.3 V and to GND. This should

common-mode voltage of 1.65 V (above the minimum required

1.5 V). This may necessitate scraping off the solder mask near

these transmission lines.

The UG-068 user guide contains similar information relevant to

the operation of the ADCLK948/PCBZ evaluation board