MIC2103YML datasheet(27/36 Pages) MICREL

27 / 36 page

Micrel, Inc.

MIC2103/04

August 2012

M9999-080712-A

PCB Layout Guidelines

Warning: To minimize EMI and output noise, follow

these layout recommendations.

PCB Layout is critical to achieve reliable, stable and

efficient performance. A ground plane is required to

control EMI and minimize the inductance in power,

signal and return paths.

The following guidelines should be followed to insure

proper operation of the MIC2103 converter.



The 1µF ceramic capacitors, which are connected to

the VDD and PVDD pins, must be located right at

the IC. The VDD pin is very noise sensitive and

placement of the capacitor is very critical. Use wide

traces to connect to the VDD and PGND pins.



The signal ground pin (GND) must be connected

directly to the ground planes. Do not route the GND

pin to the PGND pin on the top layer.



Place the IC close to the point of load (POL).



Use fat traces to route the input and output power

lines.



Signal and power grounds should be kept separate

and connected at only one location.

Input Capacitor



Place the input capacitor next.



Place the input capacitors on the same side of the

board and as close to the MOSFETs as possible.



Place several vias to the ground plane close to the

input capacitor ground terminal.



Use either X7R or X5R dielectric input capacitors.

Do not use Y5V or Z5U type capacitors.



Do not replace the ceramic input capacitor with any

other type of capacitor. Any type of capacitor can be

placed in parallel with the input capacitor.



If a Tantalum input capacitor is placed in parallel

with the input capacitor, it must be recommended for

switching regulator applications and the operating

voltage must be derated by 50%.



In “Hot-Plug” applications, a Tantalum or Electrolytic

bypass capacitor must be used to limit the over-

voltage spike seen on the input supply with power is

suddenly applied.

RC Snubber



Place the RC snubber on the same side of the board

and as close to the SW pin as possible.

Inductor



Keep the inductor connection to the switch node

(SW) short.



Do not route any digital lines underneath or close to

the inductor.



Keep the switch node (SW) away from the feedback

(FB) pin.



The SW pin should be connected directly to the

drain of the low-side MOSFET to accurate sense the

voltage across the low-side MOSFET.



To minimize noise, place a ground plane underneath

the inductor.

Output Capacitor



Use a wide trace to connect the output capacitor

ground terminal to the input capacitor ground

terminal.



Phase margin will change as the output capacitor

value and ESR changes. Contact the factory if the

output capacitor is different from what is shown in

the BOM.



The feedback trace should be separate from the

power trace and connected as close as possible to

the output capacitor. Sensing a long high-current

load trace can degrade the DC load regulation.

MOSFETs



Low-side MOSFET gate drive trace (DL pin to

MOSFET gate pin) must be short and routed over a

ground plane. The ground plane should be the

connection between the MOSFET source and

PGND.



Chose a low-side MOSFET with a high CGS/CGD ratio

and a low internal gate resistance to minimize the

effect of dv/dt inducted turn-on.



Do not put a resistor between the Low-side

MOSFET gate drive output and the gate.



Use a 4.5V VGS rated MOSFET. Its higher gate

threshold voltage is more immune to glitches than a

2.5V or 3.3V rated MOSFET. MOSFETs that are

rated for operation at less than 4.5V VGS should not

be used.

MIC2103YML Datasheet(PDF) 27 Page - Micrel Semiconductor

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