SiC403DB datasheet(13/24 Pages) VISHAY

13 / 24 page

Vishay Siliconix

SiC403A, SiC403BCD

Document Number: 62768

S12-1972-Rev. A, 27-Aug-12

www.vishay.com

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: powerictechsupport@vishay.com

When a large capacitor is placed in parallel with R1 (CTOP)

VOUT is shown by the following equation.

Enable and Power-Save Inputs

The EN/PSV input is used to enable or disable the switching

regulator. When EN/PSV is low (grounded), the switching

regulator is off and in its lowest power state. When off, the

output of the switching regulator soft-discharges the output

into a 15

 internal resistor via the V

OUT pin. When EN/PSV

is allowed to float, the pin voltage will float to 33 % of the

voltage at VDD. The switching regulator turns on with

power-save disabled and all switching is in forced continuous

mode.

When EN/PSV is high (above 44 % of the voltage at VDD),

the switching regulator turns on with power-save enabled.

The SiC403A/B P-Save operation reduces the switching

frequency according to the load for increased efficiency at

light load conditions.

Forced Continuous Mode Operation

The SiC403A/B operates the switcher in FCM (Forced

Continuous Mode) by floating the EN/PSV pin (see figure 4).

In this mode one of the power MOSFETs is always on, with

no intentional dead time other than to avoid cross-

conduction. This feature results in uniform frequency across

the full load range with the trade-off being poor efficiency at

light loads due to the high-frequency switching of the

MOSFETs. DH is gate signal to drive upper MOSFET. DL is

lower gate signal to drive lower MOSFET

Ultrasonic Power-Save Operation (SiC403A)

The SiC403A provides ultrasonic power-save operation at

light loads, with the minimum operating frequency fixed at

slightly under 25 kHz. This is accomplished by using an

internal timer that monitors the time between consecutive

high-side gate pulses. If the time exceeds 40 µs, DL drives

high to turn the low-side MOSFET on. This draws current

from VOUT through the inductor, forcing both VOUT and VFB

to fall. When VFB drops to the 600 mV threshold, the next DH

(the drive signal for the high side FET) on-time is triggered.

After the on-time is completed the high-side MOSFET is

turned off and the low-side MOSFET turns on. The low-side

MOSFET remains on until the inductor current ramps down

to zero, at which point the low-side MOSFET is turned off.

Because the on-times are forced to occur at intervals no

greater than 40 µs, the frequency will not fall far below

25 kHz. Figure 5 shows ultrasonic power-save operation.

Power-Save Operation (SiC403B)

The SiC403B provides power-save operation at light loads

with no minimum operating frequency. With power-save

enabled, the internal zero crossing comparator monitors the

inductor current via the voltage across the low-side MOSFET

during the off-time. If the inductor current falls to zero

for 8 consecutive switching cycles, the controller enters

MOSFET on each subsequent cycle provided that the

power-save operation. It will turn off the low-side MOSFET

on each subsequent cycle provided that the current crosses

zero. At this time both MOSFETs remain off until VFB drops

to the 600 mV threshold. Because the MOSFETs are off, the

load is supplied by the output capacitor.

If the inductor current does not reach zero on any switching

cycle, the controller immediately exits power-save and

returns to forced continuous mode.

Figure 6 shows power-save operation at light loads.

Figure 4 - Forced Continuous Mode Operation

OUT = 0.6 x 1 +

RIPPLE

2 x R1

2 + R1

ωCTOP

1 +

1 + (R1

ωCTOP)2

FB ripple

voltage (VFB)

Inductor

current

DC load current

FB threshold

(600 mV)

On-time

(tON)

DH on-time is triggered when

VFB reaches the FB threshold

DL drives high when on-time is completed.

DL remains high until VFB falls to the FB threshold.

Figure 5 - Ultrasonic Power-Save Operation

FB ripple

voltage (VFB)

Inductor

current

(0A)

FB threshold

(600 mV)

On-time

(tON)

DH on-time is triggered when

VFB reaches the FB threshold

After the 40 µs time-out, DL drives high if VFB

has not reached the FB threshold.

minimum fSW ~ 25 kHz

40 µs time-out

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