Fin (MHz)

SNR vs Input Frequency and External Clock Jitter

61.0

62.0

63.0

64.0

10

100

1000

35 fs

50 fs

100 fs

150 fs

200 fs

T

=

Jitter

(T

) + (T

)

Jitter,Ext.Clock_Input

Aperture_ADC

2

2

SNR

[dBc] = 20

log(2

f

t

)

Jitter

IN

-

´

p ´

´

Jitter

2

2

2

Quantization _ Noise

ThermalNoise

Jitter

ADC

SNR

SNR

SNR

SNR

[dBc]

20 log

10

10

10

20

20

20

æ

ö

æ

ö

æ

ö

= -

´

-

+

-

+

-

ç

÷

ç

÷

ç

÷

ç

÷

è

ø

è

ø

è

ø

ADS5407

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SLAS934A – MARCH 2013 – REVISED AUGUST 2013

SNR AND CLOCK JITTER

The signal to noise ratio of the ADC is limited by three different factors: the quantization noise is typically not

noticeable in pipeline converters and is 74dB for a 12bit ADC. The thermal noise limits the SNR at low input

frequencies while the clock jitter sets the SNR for higher input frequencies.

(1)

The SNR limitation due to sample clock jitter can be calculated as following:

(2)

The total clock jitter (TJitter) has three components – the internal aperture jitter (100fs for ADS5407) which is set

by the noise of the clock input buffer, the external clock jitter and the jitter from the analog input signal. It can be

calculated as following:

(3)

External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass

filters at the clock input while a faster clock slew rate improves the ADC aperture jitter.

The ADS5407 has a thermal noise of 63.8 dBFS and internal aperture jitter of 100fs. The SNR depending on

amount of external jitter for different input frequencies is shown in the following figure.

Copyright © 2013, Texas Instruments Incorporated

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