[AP4305]

Rev 0.5.0

21

The timing chart is shown below.

SDA

SCL

tBUF

tHD:SDA

tLOW tR

tHIGH

tF

tHD:DAT

tSU:DAT

tSU:STA

tSP

tSU:STO

Stop

Start

Start

Stop

VIH

VIH

VIL

VIL

SCL

1/Fscl

VIH

VIL

Figure 7. Timing chart of I2C interface

6.1.1.

Write Sequence

One-byte and multiple-byte write sequences are supported.

When the device receives its own slave address and the W bit after receiving a Start condition, it handles the

second byte as a register address and the third and following bytes as write data. When the device receives a

Stop condition after the assertion of Acknowledge in the third byte, the communication is terminated. (1-byte

write sequence). When the device receives the fourth and following bytes without receiving a Stop condition, it

automatically increments the register address in increments of one and writes the received data to the register.

The device continues writing the received data until it receives a Stop condition. (Multiple-byte write

sequence)

If the register address reaches the final address in the middle of a multiple-byte write sequence, the next

received data will be written in the address zero.

(1) 1 byte write sequence (Register Address=N)

S

W

Slave Address

A

A

Register

Address(N)

Data(N)

A P

(2) M byte write sequence (Register Address=N)

Data(N+1)

S

W

Slave Address

A

A

Register

Address(N)

Data(N)

A

A

Data(N+M-1)

A P

: Driven by master device

: Driven by AP4305

The meaning of each symbol is as follows.

S: Start condition

RS: Repeat Start condition

A: Acknowledge

NA: Non Acknowledge

P: Stop condition

R: Read bit (= 1)

W: Write bit (= 0)

Register Address (N): Register Address = address N

Data (N): Write/Read data in address N