CC2541

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SWRS110D – JANUARY 2012 – REVISED JUNE 2013

BLOCK DESCRIPTIONS

A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three

categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related

modules. In the following subsections, a short description of each module is given.

CPU and Memory

The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,

DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.

The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical

memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access

of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is

responsible for performing arbitration and sequencing between simultaneous memory accesses to the same

physical memory.

The SFR bus is drawn conceptually in Figure 9 as a common bus that connects all hardware peripherals to the

memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio

register bank, even though these are indeed mapped into XDATA memory space.

The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is

an ultralow-power SRAM that retains its contents even when the digital part is powered off (power mode 2 and

mode 3).

The 128/256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and

maps into the CODE and XDATA memory spaces.

Peripherals

Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise

programming. See User Guide for details on the flash controller.

A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory

space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing

mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be

located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers,

ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data transfers

between a single SFR or XREG address and flash/SRAM.

Each CC2541 contains a unique 48-bit IEEE address that can be used as the public device address for a

Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth

specfication.

The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which

is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the

device is in a sleep mode (power modes 1 and 2) by bringing the CC2541 back to the active mode.

The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.

Through this debug interface, it is possible to erase or program the entire flash memory, control which oscillators

are enabled, stop and start execution of the user program, execute instructions on the 8051 core, set code

breakpoints, and single-step through instructions in the code. Using these techniques, it is possible to perform in-

circuit debugging and external flash programming elegantly.

The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral

modules control certain pins or whether they are under software control, and if so, whether each pin is configured

as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects

to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.

The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or an

internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except power mode

3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode 1

or mode 2.

A built-in watchdog timer allows the CC2541 to reset itself if the firmware hangs. When enabled by software,

the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.

Copyright © 2012–2013, Texas Instruments Incorporated

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