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AD7671

–17–

DIGITAL INTERFACE

The AD7671 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7671 digital interface also accommodates both 3 V or 5 V logic

by simply connecting the OVDD supply pin of the AD7671 to the

host system interface digital supply. Finally, by using the OB/

input pin, straight binary and twos complement coding can be used.

The two signals

CS and RD control the interface. When at least

one of these signals is HIGH, the interface outputs are in high

impedance. Usually,

CS allows the selection of each AD7671 in

multicircuit applications and is held LOW in a single AD7671

design.

RD is generally used to enable the conversion result on

the data bus.

t11

CNVST

BUSY

DATA BUS

CS = RD = 0

t10

PREVIOUS CONVERSION DATA

NEW DATA

Figure 13. Master Parallel Data Timing for Reading

(Continuous Read)

PARALLEL INTERFACE

The AD7671 is configured to use the parallel interface when the

SER/

PAR is held LOW. The data can be read either after each

conversion, which is during the next acquisition phase, or during

the following conversion as shown, respectively, in Figures 14 and

15. When the data is read during the conversion, however, it is

recommended that it be read-only during the first half of the con-

version phase. That avoids any potential feedthrough between

voltage transients on the digital interface and the most critical

analog conversion circuitry.

BUSY

CURRENT

CONVERSION

DATA BUS

t12

t13

Figure 14. Slave Parallel Data Timing for Reading (Read

after Convert)

CS = 0

CNVST,

CONVERSION

t12

t13

BUSY

DATA BUS

Figure 15. Slave Parallel Data Timing for Reading (Read

during Convert)

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 16, the LSB is output on D[7:0] and the

MSB is output on D[15:8] when BYTESWAP is LOW. When

BYTESWAP is HIGH, the LSB and MSB bytes are swapped and

the LSB is output on D[15:8] and the MSB is output on D[7:0].

By connecting BYTESWAP to an address line, the 16 data bits

can be read in two bytes on either D[15:8] or D[7:0].

BYTE

PINS D[15:8]

HI-Z

HIGH BYTE

LOW BYTE

HI-Z

HIGH BYTE

LOW BYTE

HI-Z

PINS D[7:0]

Figure 16. 8-Bit Parallel Interface

SERIAL INTERFACE

The AD7671 is configured to use the serial interface when the

SER/

PAR is held HIGH. The AD7671 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on the SCLK pin. The output data

is valid on both the rising and falling edge of the data clock.

SLAVE SERIAL INTERFACE

External Clock

The AD7671 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/

INT pin is

held HIGH. In this mode, several methods can be used to read

the data. The external serial clock is gated by

CS and the data

are output when both

CS and RD are LOW. Thus, depending on

CS, the data can be read after each conversion or during the follow-

ing conversion. The external clock can be either a continuous or

discontinuous clock. A discontinuous clock can be either normally

HIGH or normally LOW when inactive. Figures 19 and 21

show the detailed timing diagrams of these methods.

REV. C

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