AD7671

–20–

To reduce performance degradation due to digital activity, a fast

discontinuous clock of at least 25 MHz when Impulse Mode is

used, 32 MHz when Normal or 40 MHz when Warp Mode is

used, is recommended to ensure that all the bits are read during

the first half of the conversion phase. It is also possible to begin

to read the data after conversion and continue to read the last bits

even after a new conversion has been initiated. That allows the use

of a slower clock speed like 18 MHz in Impulse Mode, 21 MHz

in Normal Mode, and 26 MHz in Warp Mode.

MICROPROCESSOR INTERFACING

The AD7671 is ideally suited for traditional dc measurement

applications supporting a microprocessor and ac signal processing

applications interfacing to a digital signal processor. The AD7671

is designed to interface either with a parallel 8-bit or 16-bit wide

interface or with a general-purpose Serial Port or I/O Ports on a

microcontroller. A variety of external buffers can be used with

the AD7671 to prevent digital noise from coupling into the ADC.

The following sections illustrate the use of the AD7671 with an

SPI equipped microcontroller, the ADSP-21065L and ADSP-218x

signal processors.

SPI Interface (MC68HC11)

Figure 22 shows an interface diagram between the AD7671 and an

SPI-equipped microcontroller, such as the MC68HC11. To accom-

modate the slower speed of the microcontroller, the AD7671 acts as

a slave device and data must be read after conversion. This mode

also allows the daisy-chain feature. The convert command could be

initiated in response to an internal timer interrupt. The reading of

output data, one byte at a time if necessary, could be initiated in

response to the end-of-conversion signal (BUSY going low) using

an interrupt line of the microcontroller. The serial peripheral

interface (SPI) on the MC68HC11 is configured for Master Mode

(MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit

(CPHA) = 1, and SPI interrupt enable (SPIE) = 1 by writing to

the SPI Control Register (SPCR). The IRQ is configured for edge-

sensitive-only operation (IRQE = 1 in the OPTION register).

IRQ

MC68HC11*

CNVST

AD7671*

BUSY

CS

MISO/SDI

SCK

I/O PORT

SDOUT

SCLK

INVSCLK

EXT/

INT

DVDD

*ADDITIONAL PINS OMITTED FOR CLARITY

SER/

PAR

RD

Figure 22. Interfacing the AD7671 to SPI Interface

ADSP-21065L in Master Serial Interface

As shown in Figure 23, the AD7671 can be interfaced to the

ADSP-21065L using the serial interface in Master Mode without

any glue logic required. This mode combines the advantages

of reducing the wire connections and the ability to read the

data during or after conversion at maximum speed transfer

(DIVSCLK[0:1] both low).

The AD7671 is configured for the Internal Clock Mode (EXT/

INT

LOW) and acts therefore as the master device. The convert

command can be generated by either an external low jitter oscil-

lator or, as shown, by a FLAG output of the ADSP-21065L or by

a frame output TFS of one Serial Port of the ADSP-21065L, which

can be used like a timer. The Serial Port on the ADSP-21065L

is configured for external clock (IRFS = 0), rising edge active

(CKRE = 1), external late framed sync signals (IRFS = 0,

LAFS = 1, RFSR = 1), and active HIGH (LRFS = 0). The Serial

Port of the ADSP-21065L is configured by writing to its receive

control register (SRCTL)—see ADSP-2106x SHARC User’s

Manual. Because the Serial Port within the ADSP-21065L will

be seeing a discontinuous clock, an initial word reading has to

be done after the ADSP-21065L has been reset to ensure that

the Serial Port is properly synchronized to this clock during each

following data read operation.

CNVST

SDOUT

SCLK

D1

D0

X

D15

D14

D13

12

3

14

15

16

BUSY

INVSCLK = 0

CS

EXT/

INT = 1

RD = 0

Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

REV. C