DAC8248

–11–

REV. B

AUTOMATIC DATA TRANSFER MODE

Data may be transferred automatically from the input register to

the DAC register. The first cycle loads the first data byte into

the input register; the second cycle loads the second data byte

and simultaneously transfers the full 12-bit data word to the

DAC register. It takes four cycles to load and transfer two com-

plete digital words for both DAC’s, see Figure 4 (Four Cycle

Update Timing Diagram) and the Mode Selection Table.

STROBED DATA TRANSFER MODE

Strobed data transfer allows the full 12-bit digital word to be

loaded into the input registers and transferred to the DAC regis-

ters at a later time. This transfer mode requires five cycles: four

to load two new data words into both DACs, and the fifth to

transfer all data into the DAC registers. See Figure 5 (Five Cycle

Update Timing Diagram) and the Mode Selection Table.

Strobed data transfer separating data loading and transfer op-

erations serves two functions: the DAC output updating may be

more precisely controlled, and multiple DACs in a multiple

DAC system can be updated simultaneously.

RESET

The DAC8248 comes with a RESET pin that is useful in system

calibration cycles and/or during system power-up. All registers

are reset to zero when RESET is low, and latched at zero on the

rising edge of the RESET signal when WRITE is high.

INTERFACE CONTROL LOGIC

The DAC8248’s control logic is shown in Figure 6. This cir-

cuitry interfaces with the system bus and controls the DAC

functions.

Figure 6. Input Control Logic

MODE SELECTION TABLE

DIGITAL INPUTS

REGISTER STATUS

DAC A

DAC B

Input Register

DAC

Input Register

DAC

DAC A

/B

WR

LSB

/MSB

RESET

LDAC

LSB

MSB

Register

LSB

MSB

Register

L

L

L

H

H

WR

LAT

LAT

LAT

LAT

LAT

L

L

L

H

L

WR

LAT

WR

LAT

LAT

WR

L

L

H

H

H

LAT

WR

LAT

LAT

LAT

LAT

L

L

H

H

L

LAT

WR

WR

LAT

LAT

WR

H

L

L

H

H

LAT

LAT

LAT

WR

LAT

LAT

H

L

L

H

L

LAT

LAT

WR

WR

LAT

WR

H

L

H

H

H

LAT

LAT

LAT

LAT

WR

LAT

H

L

H

H

L

LAT

LAT

WR

LAT

WR

WR

X

H

X

H

H

LAT

LAT

LAT

LAT

LAT

LAT

X

H

X

H

L

LAT

LAT

WR

LAT

LAT

WR

X

X

X

L

X

ALL REGISTERS ARE RESET TO ZEROS

XH

X

g

X

ZEROS ARE LATCHED IN ALL REGISTERS

L = Low, H = High, X = Don’t Care, WR = Registers Being Loaded, LAT = Registers Latched.