D1

R1

C2

26 pF

D2

C1

4 pF

Conversion Phase - Switch Open

Track Phase - Switch Closed

ADC081S051

SNAS309E – APRIL 2005 – REVISED MARCH 2013

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ANALOG INPUTS

An equivalent circuit of the ADC's input is shown in Figure 22. Diodes D1 and D2 provide ESD protection for the

diodes will begin to conduct, which could result in erratic operation. For this reason, the ESD diodes should not

be used to clamp the input signal.

The capacitor C1 in Figure 22 has a typical value of 4 pF, and is mainly the package pin capacitance. Resistor

R1 is the on resistance of the track / hold switch, and is typically 500

Ω. Capacitor C2 is the ADC sampling

capacitor and is typically 26 pF. The ADC will deliver best performance when driven by a low-impedance source

to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when

using the ADC to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter.

Figure 22. Equivalent Input Circuit

DIGITAL INPUTS AND OUTPUTS

The ADC digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The

allows the ADC to be interfaced with a wide range of logic levels, independent of the supply voltage.

MODES OF OPERATION

The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal

mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is

pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains

low. Once in shutdown mode, the device will stay there until CS is brought low again. By varying the ratio of time

spent in the normal and shutdown modes, a system may trade-off throughput for power consumption, with a

sample rate as low as zero.

Normal Mode

The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no

power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th

falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).

If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal

mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output

word).

Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles

have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought

high again before the start of the next conversion, which begins when CS is again brought low.

elapsed, by bringing CS low again.

Shutdown Mode

Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade

throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off.

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