ADC122S021 datasheet(5/25 Pages) TI

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ADC102S021

www.ti.com

SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013

ADC102S021 Converter Electrical Characteristics

(1) (continued)

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50

ksps to 200 ksps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Parameter

Test Conditions

Typ

Limits(1)

Units

DIGITAL OUTPUT CHARACTERISTICS

ISOURCE = 200 µA

VA − 0.03

VA − 0.5

V (min)

VOH

Output High Voltage

ISOURCE = 1 mA

VA − 0.1

ISINK = 200 µA

0.03

0.4

V (max)

VOL

Output Low Voltage

ISINK = 1 mA

0.1

IOZH, IOZL TRI-STATE Leakage Current

±0.01

±1

µA (max)

COUT

TRI-STATE Output Capacitance

pF (max)

Output Coding

Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS (CL = 10 pF)

2.7

V (min)

Supply Voltage

5.25

V (max)

VA = +5.25V,

1.3

1.8

mA (max)

fSAMPLE = 200 ksps, fIN = 40 kHz

Supply Current, Normal Mode

(Operational, CS low)

VA = +3.6V,

0.55

0.7

mA (max)

fSAMPLE = 200 ksps, fIN = 40 kHz

VA = +5.25V,

fSAMPLE = 0 ksps

Supply Current, Shutdown (CS high)

VA = +3.6V,

fSAMPLE = 0 ksps

VA = +5.25V

6.9

9.5

mW (max)

Power Consumption, Normal Mode

(Operational, CS low)

VA = +3.6V

1.94

2.5

mW (max)

VA = +5.25V

0.47

µW

Power Consumption, Shutdown (CS

high)

VA = +3.6V

0.12

µW

AC ELECTRICAL CHARACTERISTICS

0.8

MHz (min)

fSCLK

Clock Frequency

See(2)

3.2

MHz (max)

ksps (min)

Sample Rate

See(2)

200

ksps (max)

tCONV

Conversion Time

SCLK cycles

% (min)

SCLK Duty Cycle

fCLK = 3.2 MHz

% (max)

tACQ

Track/Hold Acquisition Time

Full-Scale Step Input

SCLK cycles

Throughput Time

Acquisition Time + Conversion Time

SCLK cycles

(2)

This is the frequency range over which the electrical performance is specified. The device is functional over a wider range which is

specified under Operating Ratings.

ADC102S021 Timing Specifications

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50

ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Parameter

Test Conditions

Typ

Limits(1)

Units

VA = +3.0V

−3.5

tCSU

Setup Time SCLK High to CS Falling Edge

See(2)

ns (min)

VA = +5.0V

−0.5

VA = +3.0V

+4.5

tCLH

Hold time SCLK Low to CS Falling Edge

See(2)

ns (min)

VA = +5.0V

+1.5

(1)

Tested limits are specified to Texas Instrument's AOQL (Average Outgoing Quality Level).

(2)

Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.

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