1.8V, Low-Power, 12-Bit, 250Msps

ADC for Broadband Applications

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13

System Timing Requirements

Figure 5 depicts the relationship between the clock

input and output, analog input, sampling event, and

data output. The MAX1215N samples on the rising

(falling) edge of CLKP (CLKN). Output data is valid on

the next rising (falling) edge of the DCLKP (DCLKN)

clock, but has an internal latency of 11 clock cycles.

Digital Outputs (D0P/N–D11P/N, DCLKP/N,

ORP/N) and Control Input

T/B

Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N

are LVDS compatible, and data on D0P/N–D11P/N is

presented in either binary or two’s-complement format

(Table 1). The

T/B control line is an LVCMOS-compati-

ble input, which allows the user to select the desired

output format. Pulling

T/B low outputs data in two’s

complement, and pulling it high presents data in offset

binary format on the 12-bit parallel bus.

T/B has an

internal pulldown resistor and may be left unconnected

in applications using only two’s-complement output for-

mat. All LVDS outputs provide a typical 360mV voltage

swing around a 1.24V common-mode voltage, and must

be terminated at the far end of each transmission line pair

(true and complementary) with 100Ω. Apply a 1.7V to

The MAX1215N offers an additional differential output

pair (ORP, ORN) to flag out-of-range conditions, where

out-of-range is above positive or below negative full

scale. An out-of-range condition is identified with ORP

(ORN) transitioning high (low).

Note: Although a differential LVDS output architecture

reduces single-ended transients to the supply and

ground planes, capacitive loading on the digital out-

puts should still be kept as low as possible. Using

LVDS buffers on the digital outputs of the ADC when

driving larger loads may improve overall performance

and reduce system-timing constraints.

INP

INN

SAMPLING EVENT

SAMPLING EVENT

SAMPLING EVENT

SAMPLING EVENT

SAMPLING EVENT

CLKN

CLKP

DCLKN

DCLKP

D0P/D0N–

D11P/D11N

ORP/N

N

N-11

N-10

N - 1

N + 1

N

N

N - 1

N - 9

N - 10

N - 11

N + 1

N + 1

N + 11

N + 10

N + 12

NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.

Figure 5. System and Output Timing Diagram

2.89kΩ

AGND

CLKN

CLKP

5.35kΩ

5.35kΩ

5.35kΩ

Figure 4. Simplified Clock Input Architecture