AD5165

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THEORY OF OPERATION

The AD5165 is a 256-position digitally controlled variable

resistor (VR) device.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between terminals A and

has 256 contact points accessed by the wiper terminal, plus the

B terminal contact. The 8-bit data in the RDAC latch is decoded

to select one of the 256 possible settings.

A

W

B

A

W

B

A

W

B

Figure 36. Rheostat Mode Configuration

Assuming that a 100 kΩ part is used, the wiper’s first connec-

tion starts at the B terminal for data 0x00. Because there is a

50 Ω wiper contact resistance, such a connection yields a mini-

mum of 100 Ω (2 × 50 Ω) resistance between terminals W and

B. The second connection is the first tap point, which corres-

for data 0x01. The third connection is the next tap point,

representing 880 Ω (2 × 390 Ω + 2 × 50 Ω) for data 0x02, and

so on. Each LSB data value increase moves the wiper up the

resistor ladder until the last tap point is reached at 100,100 Ω

D5

D4

D3

D7

D6

D2

D1

D0

RDAC

LATCH

AND

DECODER

A

W

B

Figure 37. AD5165 Equivalent RDAC Circuit

The general equation determining the digitally programmed

output resistance between W and B is

W

AB

WB

R

R

D

D

R

×

+

×

=

2

256

)

(

(1)

where:

D is the decimal equivalent of the binary code loaded in the

8-bit RDAC register.

the internal switch.

indicated RDAC latch codes.

D (Dec.)

Output State

255

99,710

128

50,100

Midscale

1

490

1 LSB

0

100

Zero scale (wiper contact resistance)

Note that, in the zero-scale condition, a finite wiper resistance

of 100 Ω is present. Care should be taken to limit the current

flow between W and B in this state to a maximum pulse current

of no more than 20 mA. Otherwise, degradation or possible

destruction of the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the

RDAC between the wiper W and terminal A also produces a

terminals are used, the B terminal can be opened. Setting the

and decreases as the data loaded in the latch increases in value.

The general equation for this operation is

W

AB

WA

R

R

D

D

R

×

+

×

−

=

2

256

256

)

(

(2)

latch codes.

D (Dec.)

Output State

255

490

Full scale

128

50,100

Midscale

1

99, 710

1 LSB

0

100,100

Zero scale

Typical device-to-device matching is process-lot dependent

and may vary by up to ±20%. Because the resistance element

temperature has a very low 35 ppm/°C temperature coefficient.