AD5165

Rev. 0 | Page 14 of 16

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

positive, voltage across A to B, W to A, and W to B can be at

either polarity.

A

W

B

Figure 38. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper-to-B starting at 0 V

up to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across terminals A and B divided by the 256

positions of the potentiometer divider. The general equation

valid input voltage applied to terminals A and B is

B

A

W

V

D

V

D

D

V

256

256

256

)

(

−

+

=

(3)

A more accurate calculation, which includes the effect of wiper

B

AB

WA

A

AB

WB

W

V

R

D

R

V

R

D

R

D

V

)

(

)

(

)

(

+

=

(4)

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly on

absolute values. Therefore, the temperature drift reduces to

15 ppm/°C.

3-WIRE SERIAL BUS DIGITAL INTERFACE

The AD5165 contains a 3-wire digital interface (SDI, CS, and

CLK). The 8-bit serial word must be loaded MSB first. The

format of the word is shown in Table 5.

The positive-edge sensitive CLK input requires clean transitions

to avoid clocking incorrect data into the serial input register.

Standard logic families work well. If mechanical switches are

used for product evaluation, they should be debounced by a

flip-flop or other suitable means. When CS is high, the clock

loads data into the serial register on each positive clock edge,

as shown in Figure 34.

The data setup and data hold times in the specifications table

determine the valid timing requirements. The AD5165 uses an

8-bit serial input data register word that is transferred to the

internal RDAC register when the CS line returns to logic low.

Extra MSB bits are ignored.

ESD PROTECTION

All digital inputs are protected with a series of input resistors

and parallel Zener ESD structures, shown in Figure 39 and

Figure 40. This applies to the digital input pins SDI, CLK,

and CS.

LOGIC

340

Ω

GND

Figure 39. ESD Protection of Digital Pins

A, B, W

GND

Figure 40. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

conditions for proper 3-terminal digital potentiometer oper-

ation. Supply signals present on terminals A, B, and W that

diodes, as shown in Figure 41.

GND

A

W

B

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at terminals A, B, and W (see Figure 41), it is important to

powered unintentionally and may affect the rest of the user’s

circuit. The ideal power-up sequence is in the following order: