AD1852

Rev. A | Page 12 of 20

THEORY OF OPERATION

SERIAL DATA INPUT PORT

The flexible, serial data input port of the AD1852 accepts data

in twos-complement, MSB-first format. The left channel data field

always precedes the right channel data field. The serial mode is

set by either using the external mode pins (IDPM0, Pin 21 and

IDPM1, Pin 20) or the mode select bits (Bit 4 and Bit 5) in the

SPI control register. To control the serial mode using the

external mode pins, the SPI mode select bits should be set to

zero (the default mode at power-up). To control the serial mode

using the SPI mode select bits, the external mode control pins

should be grounded.

In all modes, except for right-justified mode, the serial port

accepts an arbitrary number of bits up to 24. Extra bits do not

cause an error, but they are truncated internally. In right-

justified mode, use Bit 8 and Bit 9 of the SPI control register to

set the word length to 16 bits, 20 bits, or 24 bits. The default

mode at power-up is 24-bit mode. When the SPI control port is

not being used, the SPI pins (CLATCH, CCLK, and CDATA

[Pin 3, Pin 4, and Pin 5]) should be tied low.

SERIAL DATA INPUT MODE

The AD1852 uses two multiplexed input pins to control the

mode configuration of the input data port mode (see Table 12).

Figure 3 shows the right-justified mode (16 bits shown). LRCLK is

high for the left channel and low for the right channel. Data is

valid on the rising edge of BCLK.

In normal operation, there are 64-bit clocks per frame (or 32 per

half frame). When the SPI word length control bits (Bit 8 and

Bit 9 in the SPI control register) are set to 24 bits (0:0), the serial

port begins to accept data starting at the eighth bit clock pulse

after the LRCLK transition. When the word length control bits

clock position. In 16-bit mode, data is accepted starting at the

number of bit clocks per frame, and therefore, other data formats

are possible using the delay values previously described. For

detailed timing, see Figure 26.

and high for the right channel. Data is valid on the rising edge

of BCLK. The MSB is left justified to an LRCLK transition but

accept any number of bits up to 24.

Figure 5 shows the left-justified mode. LRCLK is high for the

left channel, and low for the right channel. Data is valid on the

rising edge of BCLK. The MSB is left justified to an LRCLK

transition, with no MSB delay. The left-justified mode can

accept any word length up to 24 bits, and any number of bit

clocks from two times the word length to 64-bit clocks per

frame.

Figure 6 shows the DSP serial port mode. LRCLK must pulse

high for at least one bit clock period before the MSB of the left

channel is valid, and LRCLK must pulse high again for at least

one bit clock period before the MSB of the right channel is

valid. Data is valid on the falling edge of BCLK. The DSP serial

port mode can be used with any word length up to 24 bits.

In this mode, it is the responsibility of the DSP to ensure that

the left data is transmitted with the first LRCLK pulse and that

synchronism is maintained from that point forward.

packed mode, where the MSB is left justified to an LRCLK

transition, and the LSB is right justified to the opposite LRCLK

transition. LRCLK is high for the left channel and low for the

right channel. Data is valid on the rising edge of BLCK. Packed

mode can be used when the AD1852 is programmed in right-

justified or left-justified mode. Packed mode is shown is Figure 7.