TAS5630B

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SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012

MODE SELECTION PINS

MODE PINS

OUTPUT

ANALOG INPUT

DESCRIPTION

CONFIGURATION

M3

M2

M1

0

0

0

Differential

2 × BTL

AD mode

0

0

1

—

—

Reserved

0

1

0

Differential

2 × BTL

BD mode

Differential single-

0

1

1

1 × BTL +2 ×SE

BD mode, BTL differential

ended

1

0

0

Single-ended

4 × SE

AD mode

1

0

1

Differential

1 × PBTL

0

0

AD mode

1

0

BD mode

1

1

0

Reserved

1

1

1

(1)

INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND).

THERMAL INFORMATION

TAS5630B

UNITS

PHD (64 Pins)

DKD (44 Pins)

Junction-to-ambient thermal resistance

8.5

9.3

Junction-to-case (top) thermal resistance

0.2

0.6

Junction-to-board thermal resistance

20.6

3.7

°C/W

Junction-to-top characterization parameter

0.2

1.3

Junction-to-board characterization parameter

0.73

3.5

Junction-to-case (bottom) thermal resistance

8.2

19.1

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

Thermal model data was performed using a 40 x 40 x 90mm heat-sink

PACKAGE

DESCRIPTION

0°C–70°C

TAS5630BPHD

64-pin HTQFP

0°C–70°C

TAS5630BDKD

44-pin PSOP3

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Copyright © 2010–2012, Texas Instruments Incorporated

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