TMS320DM6467CCUTAV datasheet(13/355 Pages) TI

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TMS320DM6467

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SPRS403H – DECEMBER 2007 – REVISED JUNE 2012

3.3.8.3

DSP Memories

The ARM has access to the following DSP memories:

•

L2 RAM

•

L1P RAM

•

L1D RAM

3.3.8.4

ARM-DSP Integration

DM6467 ARM and DSP integration features are as follows:

•

DSP visibility from ARM’s memory map, see Section 3.5, Memory Map Summary, for details

•

Boot Modes for DSP - see Device Configurations section, Section 4.4.1, DSP Boot, for details

•

ARM control of DSP boot / reset - see Device Configurations section, Section 4.4.2.4, ARM Boot, for

details

•

ARM control of DSP isolation and powerdown / powerup - see Section 4, Device Configurations, for

details

•

ARM & DSP Interrupts - see Section 7.8.1, ARM CPU Interrupts, and Section 7.8.2, DSP Interrupts, for

details

3.3.9

Peripherals

The ARM9 has access to all of the peripherals on the DM6467 device.

3.3.10 PLL Controller (PLLC)

The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for

configuring DM6467’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following

configuration and control:

•

PLL Bypass Mode

•

Set PLL multiplier parameters

•

Set PLL divider parameters

•

PLL power down

•

Oscillator power down

The PLLs are briefly described in this document in the Clocking section. For more detailed information on

the PLLs and PLL Controller register descriptions, see the TMS320DM646x DMSoC ARM Subsystem

Reference Guide (literature number SPRUEP9).

3.3.11 Power and Sleep Controller (PSC)

The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings

accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating

and power domain shut-off. Brief details on the PSC are given in Section 7.3, Power Supplies. For more

detailed information and complete register descriptions for the PSC, see the TMS320DM646x DMSoC

ARM Subsystem Reference Guide (literature number SPRUEP9).

3.3.12 ARM Interrupt Controller (AINTC)

The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ

(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this

document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the

TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9).

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